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1 parent b8089bb commit e73f716Copy full SHA for e73f716
backend/arm64/emit.mlp
@@ -165,7 +165,7 @@ let record_frame_label live dbg =
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Misc.fatal_error ("bad GC root " ^ Reg.name r)
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| { typ = Valx2; } as r ->
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(* CR mslater: (SIMD) arm64 *)
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- Misc.fatal_error ("Unexpect Valx2 type of reg " ^ Reg.name r)
+ Misc.fatal_error ("Unexpected Valx2 type of reg " ^ Reg.name r)
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| { typ = Val; loc = Unknown ; } as r ->
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Misc.fatal_error ("Unknown location " ^ Reg.name r)
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| { typ = Int | Float | Float32 | Vec128; _ } -> ())
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