Skip to content

Commit adb2b97

Browse files
committed
Rebase
1 parent 074c7f8 commit adb2b97

File tree

1 file changed

+0
-14
lines changed

1 file changed

+0
-14
lines changed

backend/regalloc/regalloc_irc_state.ml

-14
Original file line numberDiff line numberDiff line change
@@ -5,12 +5,6 @@ open! Regalloc_utils
55
open! Regalloc_irc_utils
66
module Doubly_linked_list = Flambda_backend_utils.Doubly_linked_list
77

8-
module List = struct
9-
include List
10-
11-
let is_empty = function [] -> true | _ :: _ -> false
12-
end
13-
148
module RegWorkList = ArraySet.Make (struct
159
type t = Reg.t
1610

@@ -182,11 +176,7 @@ let[@inline] reset state ~new_inst_temporaries ~new_block_temporaries =
182176
unknown_reg_work_list state.spilled_nodes;
183177
RegWorkList.clear state.spilled_nodes;
184178
RegWorkList.clear state.coalesced_nodes;
185-
<<<<<<< HEAD
186179
assert (Misc.Stdlib.List.is_empty state.select_stack);
187-
=======
188-
assert (List.is_empty state.select_stack);
189-
>>>>>>> bfa5d3cc14 (Avoid polymorphic compare.)
190180
unknown_instruction_work_list state.coalesced_moves;
191181
InstructionWorkList.clear state.coalesced_moves;
192182
unknown_instruction_work_list state.constrained_moves;
@@ -296,12 +286,8 @@ let[@inline] add_colored_nodes state reg =
296286
reg.Reg.irc_work_list <- Reg.Colored;
297287
Doubly_linked_list.add_begin state.colored_nodes reg
298288

299-
<<<<<<< HEAD
300289
let[@inline] is_empty_select_stack state =
301290
Misc.Stdlib.List.is_empty state.select_stack
302-
=======
303-
let[@inline] is_empty_select_stack state = List.is_empty state.select_stack
304-
>>>>>>> bfa5d3cc14 (Avoid polymorphic compare.)
305291

306292
let[@inline] push_select_stack state reg =
307293
reg.Reg.irc_work_list <- Reg.Select_stack;

0 commit comments

Comments
 (0)