Record live offsets of [Valx2] in the frametable

For runtime4, xmm register are below [gc_regs], use negative offsets.

Author: gretay-js

backend/amd64/emit.mlp

@@ -365,13 +365,23 @@ let record_frame_label live dbg =
   let live_offset = ref [] in
   Reg.Set.iter
     (function
-      | {typ = Val; loc = Reg r} ->
+      | {typ = Val; loc = Reg r} as reg ->
+          assert (Proc.gc_regs_offset reg = r);
           live_offset := ((r lsl 1) + 1) :: !live_offset
       | {typ = Val; loc = Stack s} as reg ->
           live_offset := slot_offset s (stack_slot_class reg.typ) :: !live_offset
+      | {typ = Valx2; loc = Reg r} as reg ->
+          let n = Proc.gc_regs_offset reg in
+          let encode n = ((n lsl 1) + 1) in
+          live_offset := encode n :: encode (n + 1) :: !live_offset
+      | {typ = Valx2; loc = Stack s} as reg ->
+          let n = slot_offset s (stack_slot_class reg.typ)  in
+          live_offset := n :: n + 1 :: !live_offset
       | {typ = Addr} as r ->
           Misc.fatal_error ("bad GC root " ^ Reg.name r)
-      | _ -> ()
+      | { typ = (Val | Valx2); loc = Unknown ; } as r ->
+        Misc.fatal_error ("Unknown location " ^ Reg.name r)
+      | { typ = Int | Float | Float32 | Vec128; _ } -> ()
     )
     live;
   record_frame_descr ~label:lbl ~frame_size:(frame_size())
@@ -2243,6 +2253,7 @@ let emit_probe_handler_wrapper p =
         (match r.typ with
         | Val -> k::acc
         | Int | Float | Vec128 | Float32 -> acc
+        | Valx2 -> k::k+1::acc
         | Addr -> Misc.fatal_error ("bad GC root " ^ Reg.name r))
       | _ -> assert false)
     saved_live

backend/amd64/proc.ml

@@ -165,7 +165,40 @@ let phys_reg ty n =
   | Int | Addr | Val -> hard_int_reg.(n)
   | Float -> hard_float_reg.(n - 100)
   | Float32 -> hard_float32_reg.(n - 100)
-  | Vec128 -> hard_vec128_reg.(n - 100)
+  | Vec128 | Valx2 -> hard_vec128_reg.(n - 100)
+
+let gc_regs_offset reg =
+  (* Given register [r], return the offset (the number of [value] slots,
+     not their size in bytes) of the register from the
+     [gc_regs] pointer during GC at runtime. Keep in sync with [amd64.S]. *)
+  let r =
+    match reg.loc with
+    | Reg r -> r
+    | Stack _ | Unknown ->
+      Misc.fatal_errorf "Unexpected register location for %d" reg.stamp
+  in
+  let reg_class = register_class reg in
+  let index = (r - first_available_register.(reg_class)) in
+  match reg_class with
+  | 0 -> index
+  | 1 ->
+    let slot_size_in_vals = 2 in
+    assert (Arch.size_vec128 / Arch.size_int = slot_size_in_vals);
+    if Config.runtime5
+    then
+      (* xmm slots are above regular slots based at [gc_regs_bucket] *)
+      let num_regular_slots =
+        (* rbp is always spilled even without frame pointers *)
+        13
+      in
+      num_regular_slots + (index * slot_size_in_vals)
+    else
+      (* xmm slots are below [gc_regs] pointer *)
+      let num_xmm_slots = 16 in
+      let offset = Int.neg (num_xmm_slots * slot_size_in_vals) in
+      offset + (index * slot_size_in_vals)
+  | _ -> assert false
+
 
 let rax = phys_reg Int 0
 let rdx = phys_reg Int 4

backend/emitaux.ml

@@ -143,14 +143,19 @@ let is_long n =
   if n > 0x3FFF_FFFF then raise (Error (Stack_frame_way_too_large n));
   n >= !Flambda_backend_flags.long_frames_threshold
 
+let is_long_stack_index n =
+  let is_reg n = n land 1 = 1 in
+  (* allows negative reg offsets in runtime4 *)
+  if is_reg n && not Config.runtime5 then false else is_long n
+
 let record_frame_descr ~label ~frame_size ~live_offset debuginfo =
   assert (frame_size land 3 = 0);
   let fd_long =
     is_long (frame_size + get_flags debuginfo)
     (* The checks below are redundant (if they fail, then frame size check above
        should have failed), but they make the safety of [emit_frame] clear. *)
     || is_long (List.length live_offset)
-    || List.exists is_long live_offset
+    || List.exists is_long_stack_index live_offset
   in
   if fd_long && not !Flambda_backend_flags.allow_long_frames
   then raise (Error (Stack_frame_too_large frame_size));

backend/proc.mli

@@ -25,6 +25,7 @@ val num_available_registers: int array
 val first_available_register: int array
 val register_name: Cmm.machtype_component -> int -> string
 val phys_reg: Cmm.machtype_component -> int -> Reg.t
+val gc_regs_offset : Reg.t -> int
 val rotate_registers: bool
 val precolored_regs : unit -> Reg.Set.t