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emit.ml
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(**************************************************************************)
(* *)
(* OCaml *)
(* *)
(* Xavier Leroy, projet Gallium, INRIA Rocquencourt *)
(* Benedikt Meurer, University of Siegen *)
(* *)
(* Copyright 2013 Institut National de Recherche en Informatique et *)
(* en Automatique. *)
(* Copyright 2012 Benedikt Meurer. *)
(* *)
(* All rights reserved. This file is distributed under the terms of *)
(* the GNU Lesser General Public License version 2.1, with the *)
(* special exception on linking described in the file LICENSE. *)
(* *)
(**************************************************************************)
[@@@ocaml.warning "+a-9-40-41-42"]
(* Emission of ARM assembly code, 64-bit mode *)
(* Correctness: carefully consider any use of [Config], [Clflags],
[Flambda_backend_flags] and shared variables.
For details, see [asmgen.mli]. *)
(* CR-soon mshinwell/mslater: needs updating for locals + effects *)
open Misc
open Arch
open Proc
open Reg
open Simple_operation
open Linear
open Emitaux
module I = Arm64_ast.Instruction_name
(* Tradeoff between code size and code speed *)
let fastcode_flag = ref true
(* Names for special regs *)
let reg_domain_state_ptr = phys_reg Int 25 (* x28 *)
let reg_trap_ptr = phys_reg Int 23 (* x26 *)
let reg_alloc_ptr = phys_reg Int 24 (* x27 *)
let reg_tmp1 = phys_reg Int 26 (* x16 *)
let reg_x8 = phys_reg Int 8 (* x8 *)
let reg_stack_arg_begin = phys_reg Int 17 (* x20 *)
let reg_stack_arg_end = phys_reg Int 18 (* x21 *)
(* Output a label *)
let label_prefix =
if macosx then "L" else ".L"
let femit_label out lbl =
femit_string out label_prefix; femit_string out (Label.to_string lbl)
(* Symbols *)
(* CR sdolan: Support local symbol definitions & references on arm64 *)
let femit_symbol out s =
if macosx then femit_string out "_";
Emitaux.femit_symbol out s
(* Object types *)
let emit_symbol_type emit_lbl_or_sym lbl_or_sym ty =
if not macosx then begin
emit_printf " .type %a, %%%a\n" emit_lbl_or_sym lbl_or_sym femit_string ty
end
let emit_symbol_size sym =
if not macosx then begin
emit_printf " .size %a, .-%a\n" femit_symbol sym femit_symbol sym
end
(* Output a pseudo-register *)
let femit_reg out = function
{loc = Reg r; typ; _} -> femit_string out (register_name typ r)
| {loc = (Stack _ | Unknown); _} -> fatal_error "Emit.emit_reg"
(* Likewise, but with the 32-bit name of the register *)
let int_reg_name_w =
[| "w0"; "w1"; "w2"; "w3"; "w4"; "w5"; "w6"; "w7";
"w8"; "w9"; "w10"; "w11"; "w12"; "w13"; "w14"; "w15";
"w19"; "w20"; "w21"; "w22"; "w23"; "w24"; "w25";
"w26"; "w27"; "w28"; "w16"; "w17" |]
let femit_wreg out = function
{loc = Reg r; _} -> femit_string out int_reg_name_w.(r)
| {loc = (Stack _ | Unknown); _} -> fatal_error "Emit.emit_wreg"
(* Layout of the stack frame *)
let stack_offset = ref 0
let num_stack_slots = Stack_class.Tbl.make 0
let prologue_required = ref false
let contains_calls = ref false
let initial_stack_offset () =
Proc.initial_stack_offset ~contains_calls:!contains_calls
~num_stack_slots
let frame_size () =
Proc.frame_size
~stack_offset:!stack_offset
~contains_calls:!contains_calls
~num_stack_slots
let slot_offset loc stack_class =
let offset =
Proc.slot_offset loc ~stack_class ~stack_offset:!stack_offset
~fun_contains_calls:!contains_calls ~fun_num_stack_slots:num_stack_slots
in
match offset with
| Bytes_relative_to_stack_pointer n -> n
| Bytes_relative_to_domainstate_pointer _ ->
Misc.fatal_errorf "Not a stack slot"
(* Output a stack reference *)
let femit_stack out r =
match r.loc with
| Stack (Domainstate n) ->
let ofs = n + Domainstate.(idx_of_field Domain_extra_params) * 8 in
Printf.fprintf out "[%a, #%a]" femit_reg reg_domain_state_ptr femit_int ofs
| Stack ((Local _ | Incoming _ | Outgoing _) as s) ->
let ofs = slot_offset s (Stack_class.of_machtype r.typ) in
Printf.fprintf out "[sp, #%a]" femit_int ofs
| Reg _ | Unknown -> fatal_error "Emit.emit_stack"
(* Output an addressing mode *)
let femit_symbol_offset out (s, ofs) =
femit_symbol out s;
if ofs > 0 then Printf.fprintf out "+%a" femit_int ofs
else if ofs < 0 then Printf.fprintf out "-%a" femit_int (-ofs)
else ()
let femit_addressing out (addr, r) =
match addr with
| Iindexed ofs ->
Printf.fprintf out "[%a, #%a]" femit_reg r femit_int ofs
| Ibased(s, ofs) ->
assert (not !Clflags.dlcode); (* see selection.ml *)
Printf.fprintf out "[%a, #:lo12:%a]" femit_reg r femit_symbol_offset (s, ofs)
(* Record live pointers at call points *)
let record_frame_label live dbg =
let lbl = Cmm.new_label () in
let live_offset = ref [] in
Reg.Set.iter
(function
| {typ = Val; loc = Reg r} ->
live_offset := ((r lsl 1) + 1) :: !live_offset
| {typ = Val; loc = Stack s} as reg ->
live_offset := slot_offset s (Stack_class.of_machtype reg.typ) :: !live_offset
| {typ = Addr} as r ->
Misc.fatal_error ("bad GC root " ^ Reg.name r)
| { typ = Valx2; } as r ->
(* CR mslater: (SIMD) arm64 *)
Misc.fatal_error ("Unexpected Valx2 type of reg " ^ Reg.name r)
| { typ = Val; loc = Unknown ; } as r ->
Misc.fatal_error ("Unknown location " ^ Reg.name r)
| { typ = Int | Float | Float32 | Vec128; _ } -> ())
live;
record_frame_descr ~label:lbl ~frame_size:(frame_size())
~live_offset:!live_offset dbg;
lbl
let frecord_frame out (live, dbg) =
let lbl = record_frame_label live dbg in Printf.fprintf out "%a:" femit_label lbl
(* Record calls to the GC -- we've moved them out of the way *)
type gc_call =
{ gc_lbl: label; (* Entry label *)
gc_return_lbl: label; (* Where to branch after GC *)
gc_frame_lbl: label } (* Label of frame descriptor *)
let call_gc_sites = ref ([] : gc_call list)
let emit_call_gc gc =
emit_printf "%a: bl %a\n" femit_label gc.gc_lbl femit_symbol "caml_call_gc";
emit_printf "%a: b %a\n" femit_label gc.gc_frame_lbl femit_label gc.gc_return_lbl
(* Record calls to local stack reallocation *)
type local_realloc_call =
{ lr_lbl: label;
lr_return_lbl: label;
lr_dbg: Debuginfo.t
}
let local_realloc_sites = ref ([] : local_realloc_call list)
let emit_local_realloc lr =
emit_printf "%a:\n" femit_label lr.lr_lbl;
emit_printf " %a\n" (femit_debug_info ~discriminator: 0) lr.lr_dbg;
emit_printf " bl %a\n" femit_symbol "caml_call_local_realloc";
emit_printf " b %a\n" femit_label lr.lr_return_lbl
(* Local stack reallocation *)
type stack_realloc = {
sc_label : Label.t; (* Label of the reallocation code. *)
sc_return : Label.t; (* Label to return to after reallocation. *)
sc_max_frame_size_in_bytes : int; (* Size for reallocation. *)
}
let stack_realloc = ref (None : stack_realloc option)
let clear_stack_realloc () =
stack_realloc := None
let emit_stack_realloc () =
match !stack_realloc with
| None -> ()
| Some { sc_label; sc_return; sc_max_frame_size_in_bytes; } ->
emit_printf "%a:\n" femit_label sc_label;
(* Pass the desired frame size on the stack, since all of the
argument-passing registers may be in use. *)
emit_printf " mov %a, #%a\n" femit_reg reg_tmp1 femit_int sc_max_frame_size_in_bytes;
emit_printf " stp %a, x30, [sp, #-16]!\n" femit_reg reg_tmp1;
emit_printf " bl %a\n" femit_symbol "caml_call_realloc_stack";
emit_printf " ldp %a, x30, [sp], #16\n" femit_reg reg_tmp1;
emit_printf " b %a\n" femit_label sc_return
(* Names of various instructions *)
let name_for_comparison = function
| Isigned Ceq -> "eq" | Isigned Cne -> "ne" | Isigned Cle -> "le"
| Isigned Cge -> "ge" | Isigned Clt -> "lt" | Isigned Cgt -> "gt"
| Iunsigned Ceq -> "eq" | Iunsigned Cne -> "ne" | Iunsigned Cle -> "ls"
| Iunsigned Cge -> "cs" | Iunsigned Clt -> "cc" | Iunsigned Cgt -> "hi"
let name_for_int_operation = function
| Iadd -> "add"
| Isub -> "sub"
| Imul -> "mul"
| Idiv -> "sdiv"
| Iand -> "and"
| Ior -> "orr"
| Ixor -> "eor"
| Ilsl -> "lsl"
| Ilsr -> "lsr"
| Iasr -> "asr"
| Iclz { arg_is_non_zero = _ } -> "clz"
| Ipopcnt -> "cnt"
| Ictz _ | Icomp _ | Imod | Imulh _-> assert false
(* Decompose an integer constant into four 16-bit shifted fragments.
Omit the fragments that are equal to "default" (16 zeros or 16 ones). *)
let decompose_int default n =
let rec decomp n pos =
if pos >= 64 then [] else begin
let frag = Nativeint.logand n 0xFFFFn
and rem = Nativeint.shift_right_logical n 16 in
if frag = default
then decomp rem (pos + 16)
else (frag, pos) :: decomp rem (pos + 16)
end
in decomp n 0
(* Load an integer constant into a register *)
let emit_movk dst (f, p) =
emit_printf " movk %a, #%a, lsl #%a\n" femit_reg dst femit_nativeint f femit_int p
let emit_intconst dst n =
if is_logical_immediate n then
emit_printf " orr %a, xzr, #%a\n" femit_reg dst femit_nativeint n
else begin
let dz = decompose_int 0x0000n n
and dn = decompose_int 0xFFFFn n in
if List.length dz <= List.length dn then begin
match dz with
| [] ->
emit_printf " mov %a, xzr\n" femit_reg dst
| (f, p) :: l ->
emit_printf " movz %a, #%a, lsl #%a\n" femit_reg dst femit_nativeint f femit_int p;
List.iter (emit_movk dst) l
end else begin
match dn with
| [] ->
emit_printf " movn %a, #0\n" femit_reg dst
| (f, p) :: l ->
let nf = Nativeint.logxor f 0xFFFFn in
emit_printf " movn %a, #%a, lsl #%a\n" femit_reg dst femit_nativeint nf femit_int p;
List.iter (emit_movk dst) l
end
end
let num_instructions_for_intconst n =
if is_logical_immediate n then 1 else begin
let dz = decompose_int 0x0000n n
and dn = decompose_int 0xFFFFn n in
max 1 (min (List.length dz) (List.length dn))
end
(* Recognize float constants appropriate for FMOV dst, #fpimm instruction:
"a normalized binary floating point encoding with 1 sign bit, 4
bits of fraction and a 3-bit exponent" *)
let is_immediate_float bits =
let exp = (Int64.(to_int (shift_right_logical bits 52)) land 0x7FF) - 1023 in
let mant = Int64.logand bits 0xF_FFFF_FFFF_FFFFL in
exp >= -3 && exp <= 4 && Int64.logand mant 0xF_0000_0000_0000L = mant
let is_immediate_float32 bits =
let exp = (Int32.(to_int (shift_right_logical bits 23)) land 0x7F) - 63 in
let mant = Int32.logand bits 0x7F_FFFFl in
exp >= -3 && exp <= 4 && Int32.logand mant 0x78_0000l = mant
(* Adjust sp (up or down) by the given byte amount *)
let emit_stack_adjustment n =
let instr = if n < 0 then "sub" else "add" in
let m = abs n in
assert (m < 0x1_000_000);
let ml = m land 0xFFF and mh = m land 0xFFF_000 in
if mh <> 0 then emit_printf " %a sp, sp, #%a\n" femit_string instr femit_int mh;
if ml <> 0 then emit_printf " %a sp, sp, #%a\n" femit_string instr femit_int ml;
if n <> 0 then cfi_adjust_cfa_offset (-n)
(* Deallocate the stack frame and reload the return address
before a return or tail call *)
let output_epilogue f =
let n = frame_size() in
if !contains_calls then
emit_printf " ldr x30, [sp, #%a]\n" femit_int (n-8);
if n > 0 then
emit_stack_adjustment n;
f();
(* reset CFA back because function body may continue *)
if n > 0 then cfi_adjust_cfa_offset n
(* Output add-immediate / sub-immediate / cmp-immediate instructions *)
let rec emit_addimm rd rs n =
if n < 0 then emit_subimm rd rs (-n)
else if n <= 0xFFF then
emit_printf " add %a, %a, #%a\n" femit_reg rd femit_reg rs femit_int n
else begin
assert (n <= 0xFFF_FFF);
let nl = n land 0xFFF and nh = n land 0xFFF_000 in
emit_printf " add %a, %a, #%a\n" femit_reg rd femit_reg rs femit_int nh;
if nl <> 0 then
emit_printf " add %a, %a, #%a\n" femit_reg rd femit_reg rd femit_int nl
end
and emit_subimm rd rs n =
if n < 0 then emit_addimm rd rs (-n)
else if n <= 0xFFF then
emit_printf " sub %a, %a, #%a\n" femit_reg rd femit_reg rs femit_int n
else begin
assert (n <= 0xFFF_FFF);
let nl = n land 0xFFF and nh = n land 0xFFF_000 in
emit_printf " sub %a, %a, #%a\n" femit_reg rd femit_reg rs femit_int nh;
if nl <> 0 then
emit_printf " sub %a, %a, #%a\n" femit_reg rd femit_reg rd femit_int nl
end
let emit_cmpimm rs n =
if n >= 0
then emit_printf " cmp %a, #%a\n" femit_reg rs femit_int n
else emit_printf " cmn %a, #%a\n" femit_reg rs femit_int (-n)
(* Name of current function *)
let function_name = ref ""
(* Entry point for tail recursive calls *)
let tailrec_entry_point = ref None
(* Pending floating-point literals *)
let float_literals = ref ([] : (int64 * label) list)
let vec128_literals = ref ([] : (Cmm.vec128_bits * label) list)
(* Label a floating-point literal *)
let add_literal p f =
try
List.assoc f !p
with Not_found ->
let lbl = Cmm.new_label() in
p := (f, lbl) :: !p;
lbl
let float_literal f = add_literal float_literals f
let vec128_literal f = add_literal vec128_literals f
(* Emit all pending literals *)
let emit_literals p align emit_literal =
if !p <> [] then begin
if macosx then
emit_printf " .section __TEXT,__literal%a,%abyte_literals\n" femit_int align femit_int align;
emit_printf " .balign %a\n" femit_int align;
List.iter emit_literal !p;
p := []
end
let emit_float_literal (f, lbl) =
emit_printf "%a:" femit_label lbl; emit_float64_directive ".quad" f
let emit_vec128_literal (({ high; low; } : Cmm.vec128_bits), lbl) =
emit_printf "%a:\n" femit_label lbl;
emit_float64_directive ".quad" low;
emit_float64_directive ".quad" high
let emit_literals () =
emit_literals float_literals size_float emit_float_literal;
emit_literals vec128_literals size_vec128 emit_vec128_literal
(* Emit code to load the address of a symbol *)
let emit_load_symbol_addr dst s =
if macosx then begin
emit_printf " adrp %a, %a%@GOTPAGE\n" femit_reg dst femit_symbol s;
emit_printf " ldr %a, [%a, %a%@GOTPAGEOFF]\n" femit_reg dst femit_reg dst femit_symbol s
end else if not !Clflags.dlcode then begin
emit_printf " adrp %a, %a\n" femit_reg dst femit_symbol s;
emit_printf " add %a, %a, #:lo12:%a\n" femit_reg dst femit_reg dst femit_symbol s
end else begin
emit_printf " adrp %a, :got:%a\n" femit_reg dst femit_symbol s;
emit_printf " ldr %a, [%a, #:got_lo12:%a]\n" femit_reg dst femit_reg dst femit_symbol s
end
(* The following functions are used for calculating the sizes of the
call GC and bounds check points emitted out-of-line from the function
body. See branch_relaxation.mli. *)
let num_call_gc_points instr =
let rec loop instr call_gc =
match instr.desc with
| Lend -> call_gc
| Lop (Alloc { mode = Heap; _ }) when !fastcode_flag ->
loop instr.next (call_gc + 1)
| Lop Poll ->
loop instr.next (call_gc + 1)
(* The following four should never be seen, since this function is run
before branch relaxation. *)
| Lop (Specific (Ifar_alloc _))
| Lop (Specific Ifar_poll) -> assert false
| Lop (Alloc { mode = (Local | Heap); _ })
| Lop (Specific
(Imuladd|Imulsub|Inegmulf|Imuladdf|Inegmuladdf|Imulsubf|Inegmulsubf|
Isqrtf|Imove32|Ishiftarith (_, _)|Ibswap _|Isignext _|Isimd _))
| Lop (Move|Spill|Reload|Opaque|Begin_region|End_region|Dls_get|Const_int _|
Const_float32 _|Const_float _|Const_symbol _|Const_vec128 _|Stackoffset _|
Load _|Store (_, _, _)|Intop _|Intop_imm (_, _)|Intop_atomic _|
Floatop (_, _)|Csel _|Reinterpret_cast _|Static_cast _|Probe_is_enabled _|
Name_for_debugger _)
| Lprologue|Lreloadretaddr|Lreturn|Lentertrap|Lpoptrap|Lcall_op _|Llabel _|
Lbranch _|Lcondbranch (_, _)|Lcondbranch3 (_, _, _)|Lswitch _|
Ladjust_stack_offset _|Lpushtrap _|Lraise _|Lstackcheck _
-> loop instr.next call_gc
in
loop instr 0
let max_out_of_line_code_offset ~num_call_gc =
if num_call_gc < 1 then 0
else begin
let size_of_call_gc = 2 in
let size_of_last_thing = size_of_call_gc in
let total_size = size_of_call_gc*num_call_gc in
let max_offset = total_size - size_of_last_thing in
assert (max_offset >= 0);
max_offset
end
module DSL : sig
val check_reg : Cmm.machtype_component -> Reg.t -> unit
val emit_reg : Reg.t -> Arm64_ast.Operand.t
val emit_reg_d : Reg.t -> Arm64_ast.Operand.t
val emit_reg_s : Reg.t -> Arm64_ast.Operand.t
val emit_reg_w : Reg.t -> Arm64_ast.Operand.t
val emit_reg_v2d : Reg.t -> Arm64_ast.Operand.t
val imm : int -> Arm64_ast.Operand.t
val ins : I.t -> Arm64_ast.Operand.t array -> unit
val simd_instr : Simd.operation -> Linear.instruction -> unit
val simd_instr_size : Simd.operation -> int
end [@warning "-32"] = struct
include Arm64_ast.DSL
let check_reg typ reg =
(* same type and not on stack *)
assert (Cmm.equal_machtype_component typ reg.typ);
assert (Reg.is_reg reg);
()
(* See [Proc.int_reg_name]. *)
let int_reg_name_to_arch_index =
[| 0; 1; 2; 3; 4; 5; 6 ; 7; (* 0 - 7 *)
8; 9; 10; 11; 12; 13; 14; 15; (* 8 - 15 *)
19; 20; 21; 22; 23; 24; 25; (* 16 - 22 *)
26; 27; 28; (* 23 - 25 *)
16; 17; |] (* 26 - 27 *)
let reg_name_to_arch_index reg_class name_index =
match reg_class with
| 0 (* general-purpose registers *) -> int_reg_name_to_arch_index.(name_index)
| 1 (* neon registers *) -> name_index
| _ -> assert false
let reg_index reg =
match reg with
| {loc = Reg r; _} ->
let reg_class = Proc.register_class reg in
let name_index = r - Proc.first_available_register.(reg_class) in
reg_name_to_arch_index reg_class name_index
| {loc = (Stack _ | Unknown); _} -> fatal_error "Emit.reg"
let emit_reg_v2s reg = reg_v2s (reg_index reg)
let emit_reg_v4s reg = reg_v4s (reg_index reg)
let emit_reg_v2d reg = reg_v2d (reg_index reg)
let emit_reg_w reg = reg_w (reg_index reg)
let emit_reg_s reg = reg_s (reg_index reg)
let emit_reg_d reg = reg_d (reg_index reg)
let emit_reg reg =
(* use machtype to select register name *)
let index = reg_index reg in
match reg.typ with
| Val | Int | Addr ->
reg_x index
| Float ->
reg_d index
| Float32 ->
reg_s index
| Vec128
| Valx2 ->
reg_q index
let check_instr (register_behavior : Simd_proc.register_behavior) i =
(* Ensure that operation size and register size match.
On arm64, operation size is encoded solely into the operands
(unlike amd64 where the opcode itself usually indicates operation size). *)
match register_behavior with
| Rf32x2_Rf32x2_to_Rf32x2 ->
(* float32x2 is represented as Float machtype *)
check_reg Float i.arg.(0);
check_reg Float i.arg.(1);
check_reg Float i.res.(0);
| Rf32x4_Rf32x4_to_Ri32x4
| Rf32x4_Rf32x4_to_Rf32x4
| Rf64x2_Rf64x2_to_Rf64x2
| Ri64x2_Ri64x2_to_Ri64x2 ->
check_reg Vec128 i.arg.(0);
check_reg Vec128 i.arg.(1);
check_reg Vec128 i.res.(0);
| Ri32x4_to_Ri32x4
| Rf32x2_to_Rf64x2
| Rf32x4_to_Rf32x4
| Rf32x4_to_Ri32x4
| Ri32x4_to_Rf32x4 ->
check_reg Vec128 i.arg.(0);
check_reg Vec128 i.res.(0)
| Rf32_Rf32_to_Rf32 ->
check_reg Float32 i.arg.(0);
check_reg Float32 i.arg.(1);
check_reg Float32 i.res.(0)
| Rf64_Rf64_to_Rf64 ->
check_reg Float i.arg.(0);
check_reg Float i.arg.(1);
check_reg Float i.res.(0)
| Rf32_to_Rf32 ->
check_reg Float32 i.arg.(0);
check_reg Float32 i.res.(0)
| Rf64_to_Rf64 ->
check_reg Float i.arg.(0);
check_reg Float i.res.(0)
| Rf32_to_Ri64 ->
check_reg Float32 i.arg.(0);
check_reg Int i.res.(0)
let src_operands ops =
(* returns a copy of [ops] without the first operand, which is assumed to be the
destination operand. *)
Array.sub ops 1 (Array.length ops - 1)
let emit_regs_binary i =
[| emit_reg i.res.(0); emit_reg i.arg.(0); emit_reg i.arg.(1) |]
let emit_regs_unary i =
[| emit_reg i.res.(0); emit_reg i.arg.(0); |]
let ins name ops = print_ins name ops |> Emitaux.emit_string
let ins_cond name cond ops = print_ins_cond name cond ops |> Emitaux.emit_string
let emit_operands (register_behavior : Simd_proc.register_behavior) i =
match register_behavior with
| Rf32x2_Rf32x2_to_Rf32x2 ->
(* Special case: f32 argument is represented by machtype Float (to avoid classifying
it as a reinterpret cast), and uses vector f32x2 register in the instruction
encoding. *)
[| emit_reg_v2s i.res.(0); emit_reg_v2s i.arg.(0); emit_reg_v2s i.arg.(1)|]
| Rf32x4_Rf32x4_to_Rf32x4 ->
[| emit_reg_v4s i.res.(0); emit_reg_v4s i.arg.(0); emit_reg_v4s i.arg.(1)|]
| Ri64x2_Ri64x2_to_Ri64x2
| Rf64x2_Rf64x2_to_Rf64x2 ->
[| emit_reg_v2d i.res.(0); emit_reg_v2d i.arg.(0); emit_reg_v2d i.arg.(1)|]
| Rf32x4_Rf32x4_to_Ri32x4 ->
[| emit_reg_v4s i.res.(0); emit_reg_v4s i.arg.(0); emit_reg_v4s i.arg.(1)|]
| Ri32x4_to_Ri32x4
| Rf32x4_to_Rf32x4
| Rf32x4_to_Ri32x4
| Ri32x4_to_Rf32x4 ->
[| emit_reg_v4s i.res.(0); emit_reg_v4s i.arg.(0); |]
| Rf32x2_to_Rf64x2 ->
[| emit_reg_v2d i.res.(0); emit_reg_v2s i.arg.(0); |]
| Rf32_Rf32_to_Rf32
| Rf64_Rf64_to_Rf64 ->
emit_regs_binary i
| Rf64_to_Rf64
| Rf32_to_Rf32
| Rf32_to_Ri64 ->
emit_regs_unary i
let simd_instr_size (op : Simd.operation) =
match op with
| Min_scalar_f64 | Max_scalar_f64 -> 2
| Min_scalar_f32 | Max_scalar_f32 -> 2
| Round_f32 _ | Round_f64 _ | Round_f32x4 _ | Round_f32_i64
| Zip1_f32 | Zip1q_f32 | Zip1q_f64 | Zip2q_f64
| Addq_f32|Subq_f32|Mulq_f32|Divq_f32|Minq_f32|Maxq_f32|Recpeq_f32|Sqrtq_f32
| Rsqrteq_f32| Cvtq_s32_of_f32|Cvtq_f32_of_s32|Cvt_f64_f32|Paddq_f32
| Fmin_f32 | Fmax_f32 | Addq_i64 | Subq_i64 | Cmp_f32 _ | Cmpz_s32 _ -> 1
let emit_rounding_mode (rm : Simd.Rounding_mode.t) : I.Rounding_mode.t =
match rm with
| Neg_inf -> I.Rounding_mode.M
| Pos_inf -> I.Rounding_mode.P
| Zero -> I.Rounding_mode.Z
| Current -> I.Rounding_mode.X
| Nearest -> I.Rounding_mode.N
let emit_float_cond (cond : Simd.Float_cond.t) : I.Float_cond.t =
match cond with
| EQ -> EQ
| GT -> GT
| LE -> LE
| LT -> LT
let emit_cond (cond : Simd.Cond.t) : I.Cond.t =
match cond with
| EQ -> EQ
| GT -> GT
| GE -> GE
| LE -> LE
| LT -> LT
let simd_instr (op : Simd.operation) i =
let b = Simd_proc.register_behavior op in
check_instr b i;
let operands = emit_operands b i in
match op with
(* min/max: generate a sequence that matches the weird semantics of amd64 instruction
"minss", even when the flag [FPCR.AH] is not set. A separate intrinsics generates
fmin/fmax arm64 instructions directly. *)
| Min_scalar_f32
| Min_scalar_f64 ->
ins I.FCMP (src_operands operands);
ins_cond I.FCSEL I.Cond.MI operands;
| Max_scalar_f32
| Max_scalar_f64 ->
ins I.FCMP (src_operands operands);
ins_cond I.FCSEL I.Cond.GT operands;
| Round_f32 rm | Round_f64 rm | Round_f32x4 rm ->
ins (I.FRINT (emit_rounding_mode rm)) operands
| Round_f32_i64 ->
ins I.FCVTNS operands
| Fmin_f32 ->
ins I.FMIN operands
| Fmax_f32 ->
ins I.FMAX operands
| Zip1_f32 | Zip1q_f32
| Zip1q_f64 ->
ins I.ZIP1 operands
| Zip2q_f64 ->
ins I.ZIP2 operands
| Addq_i64 ->
ins I.ADD operands
| Subq_i64 ->
ins I.SUB operands
| Addq_f32 -> ins I.FADD operands
| Subq_f32 -> ins I.FSUB operands
| Mulq_f32 -> ins I.FMUL operands
| Divq_f32 -> ins I.FDIV operands
| Minq_f32 -> ins I.FMIN operands
| Maxq_f32 -> ins I.FMAX operands
| Recpeq_f32 -> ins I.FRECPE operands
| Sqrtq_f32 -> ins I.FSQRT operands
| Rsqrteq_f32 -> ins I.FRSQRTE operands
| Cvtq_s32_of_f32 -> ins I.FCVT operands
| Cvtq_f32_of_s32 -> ins I.FCVT operands
| Cvt_f64_f32 -> ins I.FCVTL operands
| Paddq_f32 -> ins I.FADDP operands
| Cmp_f32 c -> ins (I.FCM (emit_float_cond c)) operands
| Cmpz_s32 c -> ins (I.CM (emit_cond c)) (Array.append operands [| imm 0; |])
end
module BR = Branch_relaxation.Make (struct
(* CR-someday mshinwell: B and BL have +/- 128Mb ranges; for the moment we
assume we will never exceed this. It would seem to be most likely to
occur for branches between functions; in this case, the linker should be
able to insert veneers anyway. (See section 4.6.7 of the document
"ELF for the ARM 64-bit architecture (AArch64)".) *)
type distance = int
module Cond_branch = struct
type t = TB | CB | Bcc
let all = [TB; CB; Bcc]
(* AArch64 instructions are 32 bits wide, so [distance] in this module
means units of 32-bit words. *)
let max_displacement = function
| TB -> 32 * 1024 / 4 (* +/- 32Kb *)
| CB | Bcc -> 1 * 1024 * 1024 / 4 (* +/- 1Mb *)
let classify_instr = function
| Lop (Alloc _)
| Lop Poll -> Some Bcc
(* The various "far" variants in [specific_operation] don't need to
return [Some] here, since their code sequences never contain any
conditional branches that might need relaxing. *)
| Lcondbranch (Itruetest, _)
| Lcondbranch (Ifalsetest, _) -> Some CB
| Lcondbranch (Iinttest _, _)
| Lcondbranch (Iinttest_imm _, _)
| Lcondbranch (Ifloattest _, _) -> Some Bcc
| Lcondbranch (Ioddtest, _)
| Lcondbranch (Ieventest, _) -> Some TB
| Lcondbranch3 _ -> Some Bcc
| Lop (Specific _|Move|Spill|Reload|Opaque|Begin_region|End_region
|Dls_get|Const_int _|
Const_float32 _|Const_float _|Const_symbol _|Const_vec128 _|Stackoffset _|
Load _|Store (_, _, _)|Intop _|Intop_imm (_, _)|Intop_atomic _|
Floatop (_, _)|Csel _|Reinterpret_cast _|Static_cast _|Probe_is_enabled _|
Name_for_debugger _)
| Lprologue|Lend|Lreloadretaddr|Lreturn|Lentertrap|Lpoptrap|Lcall_op _
| Llabel _|Lbranch _|Lswitch _|Ladjust_stack_offset _|Lpushtrap _|Lraise _
|Lstackcheck _
-> None
end
let offset_pc_at_branch = 0
let prologue_size () =
(if initial_stack_offset () > 0 then 2 else 0)
+ (if !contains_calls then 1 else 0)
let epilogue_size () =
if !contains_calls then 3 else 2
let memory_access_size (memory_chunk : Cmm.memory_chunk) =
match memory_chunk with
| Single { reg = Float64 } -> 2
| Single { reg = Float32 } -> 1
| Byte_unsigned|Byte_signed|Sixteen_unsigned|Sixteen_signed|
Thirtytwo_unsigned|Thirtytwo_signed|Word_int|Word_val|Double|
Onetwentyeight_unaligned|Onetwentyeight_aligned -> 1
let instr_size = function
| Lend -> 0
| Lprologue -> prologue_size ()
| Lop (Move | Spill | Reload) -> 1
| Lop (Const_int n) ->
num_instructions_for_intconst n
| Lop (Const_float32 _) -> 2
| Lop (Const_float _) -> 2
| Lop (Const_vec128 _) -> 2
| Lop (Const_symbol _) -> 2
| Lop (Intop_atomic _) ->
(* Never generated; builtins are not yet translated to atomics *)
assert false
| Lcall_op (Lcall_ind) -> 1
| Lcall_op (Lcall_imm _) -> 1
| Lcall_op (Ltailcall_ind) -> epilogue_size ()
| Lcall_op (Ltailcall_imm { func; _ }) ->
if func.sym_name = !function_name then 1 else epilogue_size ()
| Lcall_op (Lextcall {alloc; stack_ofs; func=_; ty_res=_; ty_args=_; returns=_; } ) ->
if Config.runtime5 && stack_ofs > 0 then 5
else if alloc then 3
else 5
| Lop (Stackoffset _) -> 2
| Lop (Load { memory_chunk; addressing_mode; is_atomic; mutability=_ }) ->
let based = match addressing_mode with Iindexed _ -> 0 | Ibased _ -> 1
and barrier = if is_atomic then 1 else 0
and single = memory_access_size memory_chunk in
based + barrier + single
| Lop (Store (memory_chunk, addressing_mode, assignment)) ->
let based = match addressing_mode with Iindexed _ -> 0 | Ibased _ -> 1
and barrier =
match memory_chunk, assignment with
| (Word_int | Word_val), true -> 1
| (Word_int | Word_val), false -> 0
| (Byte_unsigned|Byte_signed|Sixteen_unsigned|Sixteen_signed|
Thirtytwo_unsigned|Thirtytwo_signed|Single _|Double|
Onetwentyeight_unaligned|Onetwentyeight_aligned),_ -> 0
and single = memory_access_size memory_chunk in
based + barrier + single
| Lop (Alloc { mode = Local; _ }) -> 9
| Lop (Alloc { mode = Heap;_ }) when !fastcode_flag -> 5
| Lop (Specific (Ifar_alloc _)) when !fastcode_flag -> 6
| Lop Poll -> 3
| Lop (Specific Ifar_poll) -> 4
| Lop (Alloc { mode = Heap; bytes = num_bytes; _ })
| Lop (Specific (Ifar_alloc { bytes = num_bytes; _ })) ->
begin match num_bytes with
| 16 | 24 | 32 -> 1
| _ -> 1 + num_instructions_for_intconst (Nativeint.of_int num_bytes)
end
| Lop (Csel _) -> 4
| Lop (Begin_region | End_region) -> 1
| Lop (Intop (Icomp _)) -> 2
| Lop (Floatop (Float64, Icompf _)) -> 2
| Lop (Floatop (Float32, Icompf _)) -> 2
| Lop (Intop_imm (Icomp _, _)) -> 2
| Lop (Intop Imod) -> 2
| Lop (Intop (Imulh _)) -> 1
| Lop (Intop (Iclz _)) -> 1
| Lop (Intop (Ictz _)) -> 2
| Lop (Intop (Iadd|Isub|Imul|Idiv|Iand|Ior|Ixor|Ilsl|Ilsr|Iasr|Ipopcnt)) -> 1
| Lop (Intop_imm
((Iadd|Isub|Imul|Idiv|Imod|Imulh _|Iand|Ior|Ixor|Ilsl|Ilsr|Iasr
| Iclz _ | Ictz _ |Ipopcnt),_)) -> 1
| Lop (Floatop (Float64, (Iabsf | Inegf))) -> 1
| Lop (Floatop (Float32, (Iabsf | Inegf))) -> 1
| Lop (Specific Isqrtf) -> 1
| Lop (Reinterpret_cast (Value_of_int | Int_of_value |
Float_of_int64 | Int64_of_float)) -> 1
| Lop (Reinterpret_cast (Float32_of_float | Float_of_float32 |
Float32_of_int32 | Int32_of_float32)) -> 1
| Lop (Reinterpret_cast V128_of_v128) -> 1
| Lop (Static_cast (Float_of_int Float64 | Int_of_float Float64)) -> 1
| Lop (Static_cast (Float_of_int Float32 | Int_of_float Float32 |
Float_of_float32 | Float32_of_float)) -> 1
| Lop (Static_cast (Scalar_of_v128 (Int8x16 | Int16x8))) -> 2
| Lop (Static_cast (Scalar_of_v128 (Int32x4 | Int64x2 | Float32x4 | Float64x2))) -> 1
| Lop (Static_cast (V128_of_scalar _ )) -> 1
| Lop (Floatop (Float64, (Iaddf | Isubf | Imulf | Idivf))) -> 1
| Lop (Floatop (Float32, (Iaddf | Isubf | Imulf | Idivf))) -> 1
| Lop (Specific Inegmulf) -> 1
| Lop (Opaque) -> 0
| Lop (Specific (Imuladdf | Inegmuladdf | Imulsubf | Inegmulsubf)) -> 1
| Lop (Specific (Ishiftarith _)) -> 1
| Lop (Specific (Imuladd | Imulsub)) -> 1
| Lop (Specific (Ibswap { bitwidth = Sixteen } )) -> 2
| Lop (Specific (Ibswap { bitwidth = (Thirtytwo | Sixtyfour) })) -> 1
| Lop (Specific Imove32) -> 1
| Lop (Specific (Isignext _)) -> 1
| Lop (Name_for_debugger _) -> 0
| Lcall_op (Lprobe _) | Lop (Probe_is_enabled _) ->
fatal_error ("Probes not supported.")
| Lop (Dls_get) -> 1
| Lreloadretaddr -> 0
| Lreturn -> epilogue_size ()
| Llabel _ -> 0
| Lbranch _ -> 1
| Lcondbranch (tst, _) ->
begin match tst with
| Itruetest -> 1
| Ifalsetest -> 1
| Iinttest _ -> 2
| Iinttest_imm _ -> 2
| Ifloattest _ -> 2
| Ioddtest -> 1
| Ieventest -> 1
end
| Lcondbranch3 (lbl0, lbl1, lbl2) ->
1 + begin match lbl0 with None -> 0 | Some _ -> 1 end
+ begin match lbl1 with None -> 0 | Some _ -> 1 end
+ begin match lbl2 with None -> 0 | Some _ -> 1 end
| Lswitch jumptbl -> 3 + Array.length jumptbl
| Lentertrap -> 0
| Ladjust_stack_offset _ -> 0
| Lpushtrap _ -> 4
| Lpoptrap -> 1
| Lraise k ->
begin match k with
| Lambda.Raise_regular -> 1
| Lambda.Raise_reraise -> 1
| Lambda.Raise_notrace -> 4
end
| Lstackcheck _ -> 5
| Lop (Specific (Isimd simd)) ->
DSL.simd_instr_size simd
let relax_poll () =
Lop (Specific Ifar_poll)
let relax_allocation ~num_bytes ~dbginfo =
Lop (Specific (Ifar_alloc { bytes = num_bytes; dbginfo }))
end)
let name_for_float_comparison : Cmm.float_comparison -> string = function
| CFeq -> "eq"
| CFneq -> "ne"
| CFlt -> "cc"
| CFnlt -> "cs"
| CFle -> "ls"
| CFnle -> "hi"
| CFgt -> "gt"
| CFngt -> "le"
| CFge -> "ge"
| CFnge -> "lt"
(* Output the assembly code for allocation. *)
let assembly_code_for_allocation i ~local ~n ~far ~dbginfo =
if local then begin
let r = i.res.(0) in
let module DS = Domainstate in
let domain_local_sp_offset = DS.(idx_of_field Domain_local_sp) * 8 in
let domain_local_limit_offset = DS.(idx_of_field Domain_local_limit) * 8 in
let domain_local_top_offset = DS.(idx_of_field Domain_local_top) * 8 in
emit_printf " ldr %a, [%a, #%a]\n" femit_reg reg_tmp1 femit_reg reg_domain_state_ptr femit_int domain_local_limit_offset;
emit_printf " ldr %a, [%a, #%a]\n" femit_reg r femit_reg reg_domain_state_ptr femit_int domain_local_sp_offset;
emit_subimm r r n;
emit_printf " str %a, [%a, #%a]\n" femit_reg r femit_reg reg_domain_state_ptr femit_int domain_local_sp_offset;
emit_printf " cmp %a, %a\n" femit_reg r femit_reg reg_tmp1;
let lbl_call = Cmm.new_label () in
emit_printf " b.lt %a\n" femit_label lbl_call;
let lbl_after_alloc = Cmm.new_label () in
emit_printf "%a:\n" femit_label lbl_after_alloc;
emit_printf " ldr %a, [%a, #%a]\n" femit_reg reg_tmp1 femit_reg reg_domain_state_ptr femit_int domain_local_top_offset;
emit_printf " add %a, %a, %a\n" femit_reg r femit_reg r femit_reg reg_tmp1;
emit_printf " add %a, %a, #%a\n" femit_reg r femit_reg r femit_int 8;
local_realloc_sites :=
{ lr_lbl = lbl_call;
lr_dbg = i.dbg;
lr_return_lbl = lbl_after_alloc } :: !local_realloc_sites
end else begin
let lbl_frame =
record_frame_label i.live (Dbg_alloc dbginfo)
in
if !fastcode_flag then begin
let lbl_after_alloc = Cmm.new_label() in
let lbl_call_gc = Cmm.new_label() in
(* n is at most Max_young_whsize * 8, i.e. currently 0x808,
so it is reasonable to assume n < 0x1_000. This makes
the generated code simpler. *)
assert (16 <= n && n < 0x1_000 && n land 0x7 = 0);
let offset = Domainstate.(idx_of_field Domain_young_limit) * 8 in
emit_printf " ldr %a, [%a, #%a]\n" femit_reg reg_tmp1 femit_reg reg_domain_state_ptr femit_int offset;
emit_subimm reg_alloc_ptr reg_alloc_ptr n;
emit_printf " cmp %a, %a\n" femit_reg reg_alloc_ptr femit_reg reg_tmp1;
if not far then begin
emit_printf " b.lo %a\n" femit_label lbl_call_gc
end else begin
let lbl = Cmm.new_label () in
emit_printf " b.cs %a\n" femit_label lbl;
emit_printf " b %a\n" femit_label lbl_call_gc;
emit_printf "%a:\n" femit_label lbl
end;
emit_printf "%a:" femit_label lbl_after_alloc;
emit_printf " add %a, %a, #8\n" femit_reg i.res.(0) femit_reg reg_alloc_ptr;
call_gc_sites :=
{ gc_lbl = lbl_call_gc;
gc_return_lbl = lbl_after_alloc;
gc_frame_lbl = lbl_frame } :: !call_gc_sites
end else begin
begin match n with
| 16 -> emit_printf " bl %a\n" femit_symbol "caml_alloc1"
| 24 -> emit_printf " bl %a\n" femit_symbol "caml_alloc2"
| 32 -> emit_printf " bl %a\n" femit_symbol "caml_alloc3"
| _ -> emit_intconst reg_x8 (Nativeint.of_int n);
emit_printf " bl %a\n" femit_symbol "caml_allocN"
end;