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Updated Project 4/5 Documentation
- Updated documentation for Project 4 - Added documentation for Project 5
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‎Project 4 - 64-Bit Adder/behavioral_adder_64/README.md

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Test 1: Simulation results from the Verilog representation of this Behavioral Adder **(All possible combinations from 0 to 31)**
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![Project 4 Waveform for Test 1](Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_E.png)
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![Project 4 Waveform for Test 1](/Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_E.png)
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Test 2: Simulation results from the Verilog representation of this Behavioral Adder **(Two large 32-bit integers)**
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![Project 4 Waveform for Test 2](Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_F.png)
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![Project 4 Waveform for Test 2](/Project 4 - 64-Bit Adder/behavioral_adder_64/Simulation Waveforms/project4_test_F.png)
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## Source Files
2020

‎Project 4 - 64-Bit Adder/look_ahead_adder_64/README.md

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Test 1: Simulation results from the Verilog representation of this 2-Bit Look Ahead Adder **(All possible combinations from 0 to 31)**
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![Project 4 Waveform for Test 1](Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_C.png)
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![Project 4 Waveform for Test 1](/Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_C.png)
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Test 2: Simulation results from the Verilog representation of this 2-Bit Look Ahead Adder **(Two large 32-bit integers)**
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![Project 4 Waveform for Test 2](Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_D.png)
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![Project 4 Waveform for Test 2](/Project 4 - 64-Bit Adder/look_ahead_adder_64/Simulation Waveforms/project4_test_D.png)
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## Source Files
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‎Project 4 - 64-Bit Adder/ripple_adder_64/README.md

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Test 1: Simulation results from the Verilog representation of this Ripple Carry Adder **(All possible combinations from 0 to 31)**
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![Project 4 Waveform for Test 1](Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_A.png)
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![Project 4 Waveform for Test 1](/Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_A.png)
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Test 2: Simulation results from the Verilog representation of this Ripple Carry Adder **(Two large 32-bit integers)**
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![Project 4 Waveform for Test 2](Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_B.png)
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![Project 4 Waveform for Test 2](/Project 4 - 64-Bit Adder/ripple_adder_64/Simulation Waveforms/project4_test_B.png)
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## Source Files
2020

‎Project 5 - ARM LEGv8 Simulator/README.md

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# Project 5 - ARM LEGv8 Simulator
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## Objective
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This functional single cycle (non-pipelined) processor is capable of performing basic arithmetic, logic and data operations. It is based on a ARM 64-bit architecture, with 32 registers each 64-bits wide long with instruction lengths of 32-bits each.
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The basic assembly instructions of LDUR, STUR, ADD, SUB, ORR, AND, CBZ and B were to be supported by the CPU, with LDUR and STUR supporting immediate values when performing certain operations to the register values.
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During development, the group took the same assembly instructions and tested it on a PSoC 5LP (using the equivalent ARM v7 ISA) and it produced the result as the simulated ARM CPU.
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When working with the unconditional branch, instead of a written label the tested instruction contains the immediate to where the branch would have been.
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Since the ARM CPU is little endian, the instruction memory in this project was designed to have 64 8-bits for each index.
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The Data Memory was made up of 31 64-bit values to show that the values could be accessed and stored via the CPU.
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With the instruction memory, data memory and register memory located outside the CPU itself, the project could be incrementally tested and treated as independent components on a physical board.
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## Supported ISA
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The examples below use the following 'variables' to show off the functionaility for each instruction:
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- r{#}: Register # in the CPU (From 0 to 31)
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- RAM: Random Access Memory (or Data Memory)
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- PC: Program Counter
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### LDUR: Load RAM into Registers
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Example 1: LDUR r2, [r10]
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- Sudo-C code: r2 = RAM[r10]
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- Explanation: Get the value in memory with the address r10 and put that memory value into r2
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Example 2: LDUR r3, [r10, #1]
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- Sudo-C code: r3 = RAM[r10 + 1]
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- Explanation: Get the value in memory with the address r10 + immediate (1) and put that memory value into r3
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### STUR: Store Registers into RAM
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Example 1: STUR r1, [r9]
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- Sudo-C code: RAM[r9] = r1
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- Explanation: Put the value of r1 into RAM at the address of the value r9
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Example 2: STUR r4, [r7, #1]
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- Sudo-C code: RAM[r7 + 1] = r4
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- Explanation: Put the value of r4 into RAM at the address of the value r7 + immediate (1)
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### ADD: Add Registers
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Example: ADD r5, r3, r2
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- Sudo-C code: r5 = r3 + r2
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- Explanation: Add the values of r3 and r2 and put the result into r5
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*Note: This does not support immediate values. Only register-to-register operations*
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### SUB: Subtract Registers
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Example: SUB r4, r3, r2
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- Sudo-C code: r4 = r3 - r2
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- Explanation: Subtract the values of r3 and r2 and put the result into r4
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*Note: This does not support immediate values. Only register-to-register operations*
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### ORR: Bit-wise OR Registers
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Example: ORR r6, r2, r3
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- Sudo-C code: r6 = r2 | r3
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- Explanation: Bit-wise OR the values of r2 and r3 and put the result into r6
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*Note: This does not support immediate values. Only register-to-register operations*
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### AND: Bit-wise AND Registers
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Example: SUB r4, r3, r2
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- Sudo-C code: r4 = r3 & r2
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- Explanation: Bit-wise AND the values of r3 and r2 and put the result into r4
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*Note: This does not support immediate values. Only register-to-register operations*
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### CBZ: Conditional Jump (when the value in Register is zero)
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Example: CBZ r1, #2
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- Sudo-C code: if (r1 == 0) { PC = PC + 2 }
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- Explanation: If the value of r1 is zero then jump two instructions, otherwise, continue executing PC++
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### B: Unconditional (arbitrary) Jump
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Example: B #2
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- Sudo-C: PC = PC + 2
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- Explanation: Jump two instructions
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## Test Program (Instructions)
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The test program used to test the CPU runs through thirteen instructions as shown in the table below.
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| Line # | ARM Assembly | Machine Code | Hexadecimal|
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|:------:|:------------------|:---------------------------------------:|:----------:|
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| 1 | LDUR r2, [r10] | 1111 1000 0100 0000 0000 0001 0100 0010 | 0xF8400142 |
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| 2 | LDUR r3, [r10, #1]| 1111 1000 0100 0000 0001 0001 0100 0011 | 0xF8401143 |
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| 3 | SUB r4, r3, r2 | 1100 1011 0000 0010 0000 0000 0110 0100 | 0xCB020064 |
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| 4 | ADD r5, r3, r2 | 1000 1011 0000 0010 0000 0000 0110 0101 | 0x8B020065 |
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| 5 | CBZ r1, #2 | 1011 0100 0000 0000 0000 0000 0100 0001 | 0xB4000041 |
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| 6 | CBZ r0, #2 | 1011 0100 0000 0000 0000 0000 0100 0000 | 0xB4000040 |
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| 7 | LDUR r2, [r10] | 1111 1000 0100 0000 0000 0001 0100 0010 | 0xF8400142 |
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| 8 | ORR r6, r2, r3 | 1010 1010 0000 0011 0000 0000 0100 0110 | 0xAA030046 |
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| 9 | AND r7, r2, r3 | 1000 1010 0000 0011 0000 0000 0100 0111 | 0x8A030047 |
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| 10 | STUR r4, [r7, #1] | 1111 1000 0000 0000 0001 0000 1110 0100 | 0xF80010E4 |
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| 11 | B #2 | 0001 0100 0000 0000 0000 0000 0000 0011 | 0x14000003 |
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| 12 | LDUR r3, [r10, #1]| 1111 1000 0100 0000 0001 0001 0100 0011 | 0xF8401143 |
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| 13 | ADD r8, r0, r1 | 1000 1011 0000 0001 0000 0000 0000 1000 | 0x8B010008 |
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## Test Program (Register and Data Memory Setup)
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The Instruction Memory was entered into the instruction memory itself to properly show its functionality while simulated.
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The Registers were initialized with values from 0-30 with register 31 defined as 0 in the reference sheet for LEG v8.
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The Data Memory was initialized with values starting from 0-3100 with each content of memory being 100 more than the previous index with an exception of index 10 and 11 with the contents 1540 and 2117 respectively.
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## Source Directories
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- **ARM LEGv8 CPU Module** - ARM_CPU.v
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- **ARM LEGv8 Testbench** - CPU_TEST.v

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