We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent dae816d commit 7d02d87Copy full SHA for 7d02d87
README.md
@@ -1,4 +1,7 @@
1
# Verilog-Projects
2
+
3
+[](https://raw.githubusercontent.com/nextseto/Verilog-Projects/master/LICENSE)
4
5
This is a Verilog repository that contains source code for past labs and projects.
6
7
## To Run & Test
@@ -31,4 +34,8 @@ This is a Verilog repository that contains source code for past labs and project
31
34
32
35
## Fall 2016
33
36
-Coming Soon...
37
+Coming Soon...
38
39
+## License
40
41
+All **Verilog-Projects** are released under the MIT license. See LICENSE for details.
0 commit comments