netlistsvg chokes on the following JSON file generated by yosys

[mithro]

netlistsvg dies with the following error;

/home/tansell/github/nturley/netlistsvg/lib/index.js:732
            riders.forEach(function(r)
                  ^

TypeError: Cannot read property 'forEach' of undefined
    at /home/tansell/github/nturley/netlistsvg/lib/index.js:732:19
    at Array.forEach (native)
    at /home/tansell/github/nturley/netlistsvg/lib/index.js:725:23
    at Array.forEach (native)
    at createWires (/home/tansell/github/nturley/netlistsvg/lib/index.js:723:18)
    at /home/tansell/github/nturley/netlistsvg/lib/index.js:40:9
    at /home/tansell/github/nturley/netlistsvg/node_modules/jsonfile/index.js:46:5
    at /home/tansell/github/nturley/netlistsvg/node_modules/graceful-fs/graceful-fs.js:78:16
    at FSReqWrap.readFileAfterClose [as oncomplete] (fs.js:380:3)

with the following input JSON file;

{
  "creator": "Yosys 0.7+381 (git sha1 8f2638ae, gcc 6.3.0-18 -fPIC -Os)",
  "modules": {
    "CARRY4_COMPLETE": {
      "attributes": {
        "top": 1,
        "src": "sim.v:1"
      },
      "ports": {
        "CO": {
          "direction": "output",
          "bits": [ 2, 3, 4, 5 ]
        },
        "O": {
          "direction": "output",
          "bits": [ 6, 7, 8, 9 ]
        },
        "CIN": {
          "direction": "input",
          "bits": [ 10 ]
        },
        "DI": {
          "direction": "input",
          "bits": [ 11, 12, 13, 14 ]
        },
        "S": {
          "direction": "input",
          "bits": [ 15, 16, 17, 18 ]
        }
      },
      "cells": {
        "$ternary$sim.v:10$3": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": 1
          },
          "attributes": {
            "src": "sim.v:10"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 12 ],
            "B": [ 2 ],
            "S": [ 16 ],
            "Y": [ 3 ]
          }
        },
        "$ternary$sim.v:11$4": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": 1
          },
          "attributes": {
            "src": "sim.v:11"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 13 ],
            "B": [ 3 ],
            "S": [ 17 ],
            "Y": [ 4 ]
          }
        },
        "$ternary$sim.v:12$5": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": 1
          },
          "attributes": {
            "src": "sim.v:12"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 14 ],
            "B": [ 4 ],
            "S": [ 18 ],
            "Y": [ 5 ]
          }
        },
        "$ternary$sim.v:9$2": {
          "hide_name": 1,
          "type": "$mux",
          "parameters": {
            "WIDTH": 1
          },
          "attributes": {
            "src": "sim.v:9"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "S": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 11 ],
            "B": [ 10 ],
            "S": [ 15 ],
            "Y": [ 2 ]
          }
        },
        "$xor$sim.v:8$1": {
          "hide_name": 1,
          "type": "$xor",
          "parameters": {
            "A_SIGNED": 0,
            "A_WIDTH": 4,
            "B_SIGNED": 0,
            "B_WIDTH": 4,
            "Y_WIDTH": 4
          },
          "attributes": {
            "src": "sim.v:8"
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 15, 16, 17, 18 ],
            "B": [ 10, 2, 3, 4 ],
            "Y": [ 6, 7, 8, 9 ]
          }
        }
      },
      "netnames": {
        "$ternary$sim.v:10$3_Y": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
            "src": "sim.v:10"
          }
        },
        "$ternary$sim.v:11$4_Y": {
          "hide_name": 1,
          "bits": [ 4 ],
          "attributes": {
            "src": "sim.v:11"
          }
        },
        "$ternary$sim.v:12$5_Y": {
          "hide_name": 1,
          "bits": [ 5 ],
          "attributes": {
            "src": "sim.v:12"
          }
        },
        "$ternary$sim.v:9$2_Y": {
          "hide_name": 1,
          "bits": [ 2 ],
          "attributes": {
            "src": "sim.v:9"
          }
        },
        "$xor$sim.v:8$1_Y": {
          "hide_name": 1,
          "bits": [ 6, 7, 8, 9 ],
          "attributes": {
            "src": "sim.v:8"
          }
        },
        "CIN": {
          "hide_name": 0,
          "bits": [ 10 ],
          "attributes": {
            "src": "sim.v:4"
          }
        },
        "CO": {
          "hide_name": 0,
          "bits": [ 2, 3, 4, 5 ],
          "attributes": {
            "src": "sim.v:2"
          }
        },
        "DI": {
          "hide_name": 0,
          "bits": [ 11, 12, 13, 14 ],
          "attributes": {
            "src": "sim.v:5"
          }
        },
        "O": {
          "hide_name": 0,
          "bits": [ 6, 7, 8, 9 ],
          "attributes": {
            "src": "sim.v:3"
          }
        },
        "S": {
          "hide_name": 0,
          "bits": [ 15, 16, 17, 18 ],
          "attributes": {
            "src": "sim.v:6"
          }
        }
      }
    }
  }
}

It was generated from the following verilog code;

module CARRY4_COMPLETE(CO, O, CIN, DI, S);
	output [3:0] CO;
	output [3:0] O;
	input wire CIN;
	input [3:0] DI;
	input [3:0] S;

	assign O = S ^ {CO[2:0], CIN};
	assign CO[0] = S[0] ? CIN : DI[0];
	assign CO[1] = S[1] ? CO[0] : DI[1];
	assign CO[2] = S[2] ? CO[1] : DI[2];
	assign CO[3] = S[3] ? CO[2] : DI[3];
endmodule

I've tried all of;

• yosys -p "proc; write_json sim.json" sim.v
• yosys -p "flatten; proc; write_json sim.json" sim.v
• yosys -p "hierarchy -top CARRY4_COMPLETE -purge_lib; flatten; proc; write_json sim.json" sim.v

Putting some console.log statements like follows;

diff --git a/lib/index.js b/lib/index.js
index a2d705f..7f8c65a 100644
--- a/lib/index.js
+++ b/lib/index.js
@@ -714,14 +714,17 @@ function createWires(module)
     {
         n.inputPorts.forEach(function(port) {
             port.parentNode = n;
+           console.log(arrayToBitstring(port.value));
             addToDefaultDict(nets,arrayToBitstring(port.value),port);
         });
     });
     var wires = [];
+    console.log("----");
     module.nodes.forEach(function(n)
     {
         n.outputPorts.forEach(function (port) {
             port.parentNode = n;
+           console.log(arrayToBitstring(port.value));
             var riders = nets[arrayToBitstring(port.value)];
             var wire = {'drivers': [port], 'riders': riders};
             wires.push(wire);

I get the following;

,2,3,4,5,
,6,7,8,9,
,12,
,2,
,16,
,13,
,3,
,17,
,14,
,4,
,18,
,11,
,10,
,15,
,15,16,17,18,
,10,2,3,4,
,2,3,4,
,2,
,3,
,4,
,10,
,2,3,4,
,11,12,13,14,
,15,16,17,18,
----
,10,
,11,12,13,14,
,15,16,17,18,
,3,
,4,
,5,

I'm guessing that the issue is something to do with the modules?

[mithro]

Okay, the problem appears to be that I have things which are unconnected.

If I change my yosys command to yosys -p "prep -top CARRY4_COMPLETE; write_json sim.json" sim.v Yosys complains my design is not valid.

[mithro]

I do have a patch which makes netlistsvg accept the "broken" design.