Forcing bits on a bus to be ordered numerically

[benipoo]

If I run Yosys on the following Verilog module that detects if a bus is equal to zero:

always @(*)
	if(bus0 == 1)
		begin
			boolean = 1;
		end
	else
		begin
			boolean = 0;
		end

Using this Yosys command:

yosys -p 'synth -auto-top ; abc -g cmos2; write_verilog output.v' "equal_to_zero.v" -p 'write_json answer.json'

It will yield this SVG schematic, however I would like the bus bits to be in order. Is there a way to do this?

[nobodywasishere]

Just to clarify, are you using the latest release or the latest from master?