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[draft] Align samples and tests for non-DMM operation on nRF54H20
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
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4 files changed

+100
-9
lines changed

4 files changed

+100
-9
lines changed

‎samples/drivers/i2s/output/boards/nrf54h20dk_nrf54h20_cpuapp.overlay

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* Copyright (c) 2024 Nordic Semiconductor ASA
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/* i2s-node0 is the transmitter/receiver */
8+
9+
/ {
10+
aliases {
11+
i2s-tx = &tdm130;
12+
};
13+
};
14+
15+
&pinctrl {
16+
tdm130_default_alt: tdm130_default_alt {
17+
group1 {
18+
psels = <NRF_PSEL(TDM_SCK_M, 1, 3)>,
19+
<NRF_PSEL(TDM_FSYNC_M, 1, 6)>,
20+
<NRF_PSEL(TDM_SDOUT, 1, 4)>,
21+
<NRF_PSEL(TDM_SDIN, 1, 5)>,
22+
<NRF_PSEL(TDM_MCK, 1, 2)>; /* Define MCLK pin */
23+
};
24+
};
25+
};
26+
27+
&tdm130 {
28+
status = "okay";
29+
pinctrl-0 = <&tdm130_default_alt>;
30+
pinctrl-names = "default";
31+
memory-regions = <&cpuapp_dma_region>;
32+
mck-frequency = <6144000>;
33+
mck-clock-source = "ACLK";
34+
sck-clock-source = "ACLK";
35+
};
36+
37+
&audiopll {
38+
status = "okay";
39+
frequency = <NRFS_AUDIOPLL_FREQ_AUDIO_44K1>;
40+
};
41+
// #define NRFS_AUDIOPLL_FREQ_AUDIO_44K1 11289591

‎samples/drivers/i2s/output/src/main.c

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#include <zephyr/kernel.h>
99
#include <zephyr/drivers/i2s.h>
1010
#include <zephyr/sys/iterable_sections.h>
11+
#include <zephyr/linker/devicetree_regions.h>
1112

1213
#define SAMPLE_NO 64
1314

@@ -40,7 +41,7 @@ static void fill_buf(int16_t *tx_block, int att)
4041
}
4142
}
4243

43-
#define NUM_BLOCKS 20
44+
#define NUM_BLOCKS 5
4445
#define BLOCK_SIZE (2 * sizeof(data))
4546

4647
#ifdef CONFIG_NOCACHE_MEMORY
@@ -49,8 +50,20 @@ static void fill_buf(int16_t *tx_block, int att)
4950
#define MEM_SLAB_CACHE_ATTR
5051
#endif /* CONFIG_NOCACHE_MEMORY */
5152

53+
#define TDM(idx) DT_NODELABEL(tdm##idx)
54+
#define TDM_PROP(idx, prop) DT_PROP(TDM(idx), prop)
55+
#define TDM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(TDM(idx), prop)
56+
57+
#define TDM_MEMORY_SECTION(idx) \
58+
COND_CODE_1(TDM_HAS_PROP(idx, memory_regions), \
59+
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
60+
DT_PHANDLE(TDM(idx), memory_regions)))))), \
61+
())
62+
63+
#define BUFFER_MEM_REGION __attribute__((__section__("cpuapp_dma_region")))
64+
5265
static char MEM_SLAB_CACHE_ATTR __aligned(WB_UP(32))
53-
_k_mem_slab_buf_tx_0_mem_slab[(NUM_BLOCKS) * WB_UP(BLOCK_SIZE)];
66+
_k_mem_slab_buf_tx_0_mem_slab[(NUM_BLOCKS) * WB_UP(BLOCK_SIZE)] TDM_MEMORY_SECTION(130);
5467

5568
static STRUCT_SECTION_ITERABLE(k_mem_slab, tx_0_mem_slab) =
5669
Z_MEM_SLAB_INITIALIZER(tx_0_mem_slab, _k_mem_slab_buf_tx_0_mem_slab,
@@ -70,8 +83,8 @@ int main(void)
7083
}
7184
/* Configure I2S stream */
7285
i2s_cfg.word_size = 16U;
73-
i2s_cfg.channels = 2U;
74-
i2s_cfg.format = I2S_FMT_DATA_FORMAT_I2S;
86+
i2s_cfg.channels = 4U;
87+
i2s_cfg.format = I2S_FMT_DATA_FORMAT_PCM_SHORT;
7588
i2s_cfg.frame_clk_freq = 44100;
7689
i2s_cfg.block_size = BLOCK_SIZE;
7790
i2s_cfg.timeout = 2000;

‎tests/drivers/i2s/i2s_api/src/common.c

Lines changed: 25 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,32 @@
88
#include <zephyr/ztest.h>
99
#include <zephyr/drivers/i2s.h>
1010
#include "i2s_api_test.h"
11+
#include <zephyr/linker/devicetree_regions.h>
1112

12-
K_MEM_SLAB_DEFINE(rx_mem_slab, BLOCK_SIZE, NUM_RX_BLOCKS, 32);
13-
K_MEM_SLAB_DEFINE(tx_mem_slab, BLOCK_SIZE, NUM_TX_BLOCKS, 32);
13+
#define TDM(idx) DT_NODELABEL(tdm##idx)
14+
#define TDM_PROP(idx, prop) DT_PROP(TDM(idx), prop)
15+
#define TDM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(TDM(idx), prop)
16+
17+
18+
#define TDM_MEMORY_SECTION(idx) \
19+
COND_CODE_1(TDM_HAS_PROP(idx, memory_regions), \
20+
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
21+
DT_PHANDLE(TDM(idx), memory_regions)))))), \
22+
())
23+
24+
#define BUFFER_MEM_REGION __attribute__((__section__("cpuapp_dma_region")))
25+
26+
char __aligned(WB_UP(32))
27+
_k_mem_slab_buf_rx_mem_slab[(NUM_RX_BLOCKS + 2) * WB_UP(BLOCK_SIZE)] TDM_MEMORY_SECTION(130);
28+
STRUCT_SECTION_ITERABLE(k_mem_slab, rx_mem_slab) =
29+
Z_MEM_SLAB_INITIALIZER(rx_mem_slab, _k_mem_slab_buf_rx_mem_slab,
30+
WB_UP(BLOCK_SIZE), NUM_RX_BLOCKS + 2);
31+
32+
char __aligned(WB_UP(32))
33+
_k_mem_slab_buf_tx_mem_slab[(NUM_TX_BLOCKS) * WB_UP(BLOCK_SIZE)] TDM_MEMORY_SECTION(130);
34+
STRUCT_SECTION_ITERABLE(k_mem_slab, tx_mem_slab) =
35+
Z_MEM_SLAB_INITIALIZER(tx_mem_slab, _k_mem_slab_buf_tx_mem_slab,
36+
WB_UP(BLOCK_SIZE), NUM_TX_BLOCKS);
1437

1538
/* The data_l represent a sine wave */
1639
ZTEST_DMEM int16_t data_l[SAMPLE_NO] = {

‎tests/drivers/i2s/i2s_speed/src/test_i2s_speed.c

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <zephyr/ztest.h>
1010
#include <zephyr/drivers/i2s.h>
1111
#include <zephyr/sys/iterable_sections.h>
12+
#include <zephyr/linker/devicetree_regions.h>
1213

1314
#define I2S_DEV_NODE_RX DT_ALIAS(i2s_node0)
1415
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
@@ -17,7 +18,7 @@
1718
#define I2S_DEV_NODE_TX DT_ALIAS(i2s_node0)
1819
#endif
1920

20-
#define NUM_BLOCKS 20
21+
#define NUM_BLOCKS 5
2122
#define SAMPLE_NO 64
2223

2324
/* The data_l represent a sine wave */
@@ -58,14 +59,27 @@ static int16_t data_r[SAMPLE_NO] = {
5859
* RX blocks to satisfy this requirement
5960
*/
6061

62+
#define TDM(idx) DT_NODELABEL(tdm##idx)
63+
#define TDM_PROP(idx, prop) DT_PROP(TDM(idx), prop)
64+
#define TDM_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(TDM(idx), prop)
65+
66+
67+
#define TDM_MEMORY_SECTION(idx) \
68+
COND_CODE_1(TDM_HAS_PROP(idx, memory_regions), \
69+
(__attribute__((__section__(LINKER_DT_NODE_REGION_NAME( \
70+
DT_PHANDLE(TDM(idx), memory_regions)))))), \
71+
())
72+
73+
#define BUFFER_MEM_REGION __attribute__((__section__("cpuapp_dma_region")))
74+
6175
char MEM_SLAB_CACHE_ATTR __aligned(WB_UP(32))
62-
_k_mem_slab_buf_rx_0_mem_slab[(NUM_BLOCKS + 2) * WB_UP(BLOCK_SIZE)];
76+
_k_mem_slab_buf_rx_0_mem_slab[(NUM_BLOCKS + 2) * WB_UP(BLOCK_SIZE)] TDM_MEMORY_SECTION(130);
6377
STRUCT_SECTION_ITERABLE(k_mem_slab, rx_0_mem_slab) =
6478
Z_MEM_SLAB_INITIALIZER(rx_0_mem_slab, _k_mem_slab_buf_rx_0_mem_slab,
6579
WB_UP(BLOCK_SIZE), NUM_BLOCKS + 2);
6680

6781
char MEM_SLAB_CACHE_ATTR __aligned(WB_UP(32))
68-
_k_mem_slab_buf_tx_0_mem_slab[(NUM_BLOCKS) * WB_UP(BLOCK_SIZE)];
82+
_k_mem_slab_buf_tx_0_mem_slab[(NUM_BLOCKS) * WB_UP(BLOCK_SIZE)] TDM_MEMORY_SECTION(130);
6983
STRUCT_SECTION_ITERABLE(k_mem_slab, tx_0_mem_slab) =
7084
Z_MEM_SLAB_INITIALIZER(tx_0_mem_slab, _k_mem_slab_buf_tx_0_mem_slab,
7185
WB_UP(BLOCK_SIZE), NUM_BLOCKS);

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