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amba/stream_meta: Add AXI4-Stream metadata packer/unpacker
Add new stream_meta subset with components for packing and unpacking AXI4-Stream metadata (ID, Dest, User) as frame prefixes: - axi4_stream_meta_packer: Extracts metadata from first beat of each frame and serializes as a prefix in the output stream - axi4_stream_meta_unpacker: Deserializes metadata prefix and applies to all beats of the output frame
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‎lib/nsl_amba/Makefile‎

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@@ -15,4 +15,5 @@ packages += axi_apb
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packages += stream_traffic
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packages += stream_to_udp
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packages += stream_to_tcp
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packages += stream_meta
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nsl_amba-ghdl-flags += -Wno-hide

‎lib/nsl_amba/stream_meta/Makefile‎

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vhdl-sources += stream_meta.pkg.vhd
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vhdl-sources += axi4_stream_meta_packer.vhd
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vhdl-sources += axi4_stream_meta_unpacker.vhd
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deps += nsl_amba.axi4_stream
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deps += nsl_data.bytestream
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deps += nsl_data.endian
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deps += nsl_logic.bool

‎lib/nsl_amba/stream_meta/axi4_stream_meta_packer.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library nsl_amba, nsl_data, nsl_logic;
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use nsl_amba.axi4_stream.all;
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use nsl_data.bytestream.all;
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use nsl_data.endian.all;
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use nsl_logic.bool.all;
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entity axi4_stream_meta_packer is
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generic(
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in_config_c : config_t;
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out_config_c : config_t;
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meta_elements_c : string := "iou";
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endian_c : endian_t := ENDIAN_BIG
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);
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port(
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clock_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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in_i : in master_t;
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in_o : out slave_t;
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out_o : out master_t;
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out_i : in slave_t
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);
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begin
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assert in_config_c.data_width = out_config_c.data_width
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report "Input and output data widths must be equal"
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severity failure;
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assert in_config_c.has_last
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report "Input configuration must have last signal"
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severity failure;
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assert out_config_c.has_last
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report "Output configuration must have last signal"
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severity failure;
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assert in_config_c.has_ready
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report "Input configuration must have ready signal"
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severity failure;
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assert out_config_c.has_ready
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report "Output configuration must have ready signal"
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severity failure;
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end entity;
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architecture beh of axi4_stream_meta_packer is
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constant meta_bits_c : natural := vector_length(in_config_c, meta_elements_c);
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constant meta_bytes_c : natural := (meta_bits_c + 7) / 8;
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constant padding_bits_c : natural := meta_bytes_c * 8 - meta_bits_c;
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constant meta_config_c : buffer_config_t := buffer_config(out_config_c, meta_bytes_c);
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type state_t is (
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ST_RESET,
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ST_IDLE,
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ST_META,
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ST_DATA
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);
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type regs_t is
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record
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state: state_t;
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meta: buffer_t;
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end record;
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signal r, rin: regs_t;
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begin
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regs: process(clock_i, reset_n_i) is
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begin
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if rising_edge(clock_i) then
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r <= rin;
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end if;
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if reset_n_i = '0' then
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r.state <= ST_RESET;
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end if;
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end process;
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transition: process(r, in_i, out_i) is
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constant padding_c : std_ulogic_vector(padding_bits_c-1 downto 0) := (others => '0');
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variable meta_vector : std_ulogic_vector(meta_bits_c-1 downto 0);
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variable meta_padded : std_ulogic_vector(meta_bytes_c * 8 - 1 downto 0);
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variable meta_bytes : byte_string(0 to meta_bytes_c-1);
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begin
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rin <= r;
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case r.state is
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when ST_RESET =>
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rin.state <= ST_IDLE;
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when ST_IDLE =>
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if is_valid(in_config_c, in_i) then
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-- Sample metadata from first beat (master holds it stable)
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if meta_bits_c > 0 then
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meta_vector := vector_pack(in_config_c, meta_elements_c, in_i);
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meta_padded := padding_c & meta_vector;
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meta_bytes := to_endian(unsigned(meta_padded), endian_c);
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rin.meta <= reset(meta_config_c, meta_bytes);
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rin.state <= ST_META;
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else
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-- No metadata to pack, go straight to data
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rin.state <= ST_DATA;
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end if;
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end if;
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when ST_META =>
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if is_ready(out_config_c, out_i) then
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rin.meta <= shift(meta_config_c, r.meta);
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if is_last(meta_config_c, r.meta) then
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rin.state <= ST_DATA;
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end if;
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end if;
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when ST_DATA =>
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if is_valid(in_config_c, in_i) and is_ready(out_config_c, out_i) and is_last(in_config_c, in_i) then
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rin.state <= ST_IDLE;
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end if;
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end case;
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end process;
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mealy: process(r, in_i, out_i) is
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begin
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in_o <= accept(in_config_c, false);
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out_o <= transfer_defaults(out_config_c);
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case r.state is
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when ST_RESET =>
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null;
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when ST_IDLE =>
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null;
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when ST_META =>
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-- Send metadata prefix
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out_o <= next_beat(meta_config_c, r.meta, last => false);
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when ST_DATA =>
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-- Forward data beats
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out_o <= transfer(out_config_c, in_config_c, in_i);
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in_o <= out_i;
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end case;
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end process;
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end architecture;

‎lib/nsl_amba/stream_meta/axi4_stream_meta_unpacker.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library nsl_amba, nsl_data, nsl_logic;
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use nsl_amba.axi4_stream.all;
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use nsl_data.bytestream.all;
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use nsl_data.endian.all;
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use nsl_logic.bool.all;
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entity axi4_stream_meta_unpacker is
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generic(
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in_config_c : config_t;
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out_config_c : config_t;
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meta_elements_c : string := "iou";
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endian_c : endian_t := ENDIAN_BIG
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);
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port(
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clock_i : in std_ulogic;
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reset_n_i : in std_ulogic;
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in_i : in master_t;
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in_o : out slave_t;
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out_o : out master_t;
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out_i : in slave_t
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);
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begin
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assert in_config_c.data_width = out_config_c.data_width
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report "Input and output data widths must be equal"
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severity failure;
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assert in_config_c.has_last
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report "Input configuration must have last signal"
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severity failure;
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assert out_config_c.has_last
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report "Output configuration must have last signal"
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severity failure;
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assert in_config_c.has_ready
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report "Input configuration must have ready signal"
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severity failure;
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assert out_config_c.has_ready
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report "Output configuration must have ready signal"
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severity failure;
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end entity;
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architecture beh of axi4_stream_meta_unpacker is
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constant meta_bits_c : natural := vector_length(out_config_c, meta_elements_c);
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constant meta_bytes_c : natural := (meta_bits_c + 7) / 8;
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constant padding_bits_c : natural := meta_bytes_c * 8 - meta_bits_c;
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constant meta_config_c : buffer_config_t := buffer_config(in_config_c, meta_bytes_c);
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type state_t is (
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ST_RESET,
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ST_META,
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ST_DATA
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);
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type regs_t is
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record
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state: state_t;
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meta: buffer_t;
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meta_beat: master_t;
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end record;
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signal r, rin: regs_t;
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begin
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regs: process(clock_i, reset_n_i) is
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begin
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if rising_edge(clock_i) then
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r <= rin;
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end if;
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if reset_n_i = '0' then
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r.state <= ST_RESET;
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end if;
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end process;
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transition: process(r, in_i, out_i) is
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variable meta_bytes : byte_string(0 to meta_bytes_c-1);
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variable meta_padded : std_ulogic_vector(meta_bytes_c * 8 - 1 downto 0);
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variable meta_vector : std_ulogic_vector(meta_bits_c-1 downto 0);
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begin
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rin <= r;
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case r.state is
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when ST_RESET =>
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if meta_bits_c > 0 then
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rin.meta <= reset(meta_config_c);
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rin.state <= ST_META;
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else
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-- No metadata to unpack, go straight to data
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rin.state <= ST_DATA;
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end if;
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when ST_META =>
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if is_valid(in_config_c, in_i) then
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rin.meta <= shift(meta_config_c, r.meta, in_i);
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if is_last(meta_config_c, r.meta, in_i) then
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-- Extract and unpack metadata
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meta_bytes := bytes(meta_config_c, shift(meta_config_c, r.meta, in_i));
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meta_padded := std_ulogic_vector(from_endian(meta_bytes, endian_c));
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meta_vector := meta_padded(meta_bits_c-1 downto 0);
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rin.meta_beat <= vector_unpack(out_config_c, meta_elements_c, meta_vector);
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rin.state <= ST_DATA;
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end if;
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end if;
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when ST_DATA =>
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if is_valid(in_config_c, in_i) and is_ready(out_config_c, out_i) and is_last(in_config_c, in_i) then
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if meta_bits_c > 0 then
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rin.meta <= reset(meta_config_c);
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rin.state <= ST_META;
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end if;
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end if;
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end case;
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end process;
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mealy: process(r, in_i, out_i) is
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variable out_v : master_t;
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begin
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in_o <= accept(in_config_c, false);
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out_o <= transfer_defaults(out_config_c);
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case r.state is
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when ST_RESET =>
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null;
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when ST_META =>
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-- Accept metadata bytes
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in_o <= accept(in_config_c, true);
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when ST_DATA =>
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-- Forward data beats with extracted metadata
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out_v := transfer(out_config_c, in_config_c, in_i);
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-- Apply extracted metadata
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out_v.id := r.meta_beat.id;
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out_v.dest := r.meta_beat.dest;
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out_v.user := r.meta_beat.user;
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out_o <= out_v;
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in_o <= out_i;
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end case;
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end process;
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end architecture;

‎lib/nsl_amba/stream_meta/stream_meta.pkg.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
3+
use ieee.numeric_std.all;
4+
5+
library nsl_amba, nsl_data;
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use nsl_amba.axi4_stream.all;
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use nsl_data.endian.all;
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-- This package provides components for handling AXI4-Stream metadata
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package stream_meta is
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-- Takes one AXI4-Stream as input and produces one AXI4-Stream as output.
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-- Input stream may have metadata (ID, Dest, User).
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-- Metadata are assumed constant for a complete frame.
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-- Metadata from the first beat of every frame are extracted and serialized
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-- as a prefix in the output frame.
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-- Output configuration may have any data width.
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-- Backpressure (ready) and framing (last) should be present on both configurations.
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component axi4_stream_meta_packer is
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generic(
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in_config_c : config_t;
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out_config_c : config_t;
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meta_elements_c : string := "iou";
24+
endian_c : endian_t := ENDIAN_BIG
25+
);
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port(
27+
clock_i : in std_ulogic;
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reset_n_i : in std_ulogic;
29+
30+
in_i : in master_t;
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in_o : out slave_t;
32+
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out_o : out master_t;
34+
out_i : in slave_t
35+
);
36+
end component;
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-- Takes one AXI4-Stream with packed metadata prefix as input and produces
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-- one AXI4-Stream as output.
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-- Extracts metadata from prefix bytes and applies them to all beats of the
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-- output frame.
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-- Input configuration may have any data width.
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-- Backpressure (ready) and framing (last) should be present on both configurations.
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component axi4_stream_meta_unpacker is
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generic(
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in_config_c : config_t;
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out_config_c : config_t;
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meta_elements_c : string := "iou";
49+
endian_c : endian_t := ENDIAN_BIG
50+
);
51+
port(
52+
clock_i : in std_ulogic;
53+
reset_n_i : in std_ulogic;
54+
55+
in_i : in master_t;
56+
in_o : out slave_t;
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out_o : out master_t;
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out_i : in slave_t
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);
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end component;
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end package;

‎tests/amba/Makefile‎

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@@ -15,6 +15,7 @@ tb += axi4_mm_types
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tb += axi4_stream_cdc
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tb += axi4_stream_fifo
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tb += axi4_stream_flusher
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tb += axi4_stream_meta
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tb += axi4_stream_narrower
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tb += axi4_stream_types
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tb += axi4_stream_widener

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