coresight/dp_transactor: Externalize ticker

This allows to reuse dp_transactor in contexts where ticker is external

Author: nipo

lib/nsl_coresight/transactor/Makefile

@@ -4,3 +4,4 @@ vhdl-sources += dp_framed_transactor.vhd
 deps += nsl_bnoc.framed
 deps += nsl_io.io
 deps += nsl_coresight.swd
+deps += nsl_event.tick

lib/nsl_coresight/transactor/dp_framed_transactor.vhd

@@ -2,7 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-library nsl_bnoc, nsl_coresight, nsl_io;
+library nsl_bnoc, nsl_coresight, nsl_io, nsl_event;
 use nsl_coresight.transactor.all;
 
 entity dp_framed_transactor is
@@ -54,11 +54,15 @@ architecture rtl of dp_framed_transactor is
 
     data            : std_ulogic_vector(31 downto 0);
 
+    divisor         : unsigned(15 downto 0);
+
     srst_drive : std_ulogic;
   end record;
 
   signal r, rin : regs_t;
 
+  signal tick_s : std_ulogic;
+
 begin
 
   reg: process (clock_i)
@@ -109,7 +113,12 @@ begin
           rin.data <= cmd_i.data & r.data(31 downto 8);
           rin.last <= cmd_i.last;
           if r.cycle = 0 then
-            rin.state <= STATE_SWD_CMD;
+            if std_match(r.cmd, DP_CMD_DIVISOR) then
+              rin.divisor <= unsigned(cmd_i.data & r.data(31 downto 24));
+              rin.state <= STATE_RSP_PUT;
+            else
+              rin.state <= STATE_SWD_CMD;
+            end if;
           end if;
         end if;
 
@@ -194,11 +203,21 @@ begin
     end case;
   end process;
 
+  tick_gen: nsl_event.tick.tick_generator_integer
+    port map(
+      clock_i => clock_i,
+      reset_n_i => reset_n_i,
+      period_m1_i => r.divisor,
+      tick_o => tick_s
+      );
+
   swd_port: dp_transactor
     port map(
       reset_n_i => reset_n_i,
       clock_i => clock_i,
 
+      tick_i => tick_s,
+      
       cmd_valid_i => s_swd_cmd_valid,
       cmd_ready_o => s_swd_cmd_ready,
       cmd_data_i.op => r.cmd,

lib/nsl_coresight/transactor/dp_transactor.vhd

@@ -10,6 +10,8 @@ entity dp_transactor is
     clock_i      : in  std_ulogic;
     reset_n_i   : in  std_ulogic;
 
+    tick_i : in std_ulogic;
+    
     cmd_valid_i  : in  std_ulogic;
     cmd_ready_o  : out std_ulogic;
     cmd_data_i : in  dp_cmd_data;
@@ -58,9 +60,6 @@ architecture rtl of dp_transactor is
     turnaround    : natural range 0 to 3;
     cycle_count   : natural range 0 to 63;
 
-    divisor       : unsigned(15 downto 0);
-    counter       : unsigned(15 downto 0);
-
     data          : std_ulogic_vector(31 downto 0);
     op            : std_ulogic_vector(7 downto 0);
     run_val       : std_ulogic;
@@ -90,7 +89,7 @@ begin
     end if;
   end process;
 
-  transition: process (r, cmd_valid_i, cmd_data_i, rsp_ready_i, swd_i)
+  transition: process (r, cmd_valid_i, cmd_data_i, rsp_ready_i, swd_i, tick_i)
     variable swclk_falling : boolean;
     variable swclk_rising : boolean;
   begin
@@ -103,10 +102,7 @@ begin
         null;
 
       when others =>
-        rin.counter <= r.counter - 1;
-
-        if r.counter = (r.counter'range => '0') then
-          rin.counter <= r.divisor;
+        if tick_i = '1' then
           rin.swd.clk <= not r.swd.clk;
           swclk_falling := r.swd.clk = '1';
           swclk_rising := r.swd.clk = '0';
@@ -119,8 +115,6 @@ begin
         rin.swd.clk <= '0';
         rin.swd.dio.v <= '0';
         rin.turnaround <= 0;
-        rin.divisor <= (others => '1');
-        rin.counter <= (others => '0');
 
       when ST_CMD_GET =>
         if cmd_valid_i = '1' then
@@ -139,10 +133,6 @@ begin
           rin.state <= ST_RUN;
           rin.run_val <= r.op(6);
 
-        elsif std_match(r.op, DP_CMD_DIVISOR) then
-          rin.divisor <= unsigned(r.data(31 downto 16));
-          rin.state <= ST_RSP_PUT;
-
         elsif std_match(r.op, DP_CMD_BITBANG) then
           rin.cycle_count <= to_integer(unsigned(r.op(4 downto 0)));
           rin.state <= ST_BITBANG;

lib/nsl_coresight/transactor/transactor.pkg.vhd

@@ -65,6 +65,8 @@ package transactor is
       clock_i     : in  std_ulogic;
       reset_n_i   : in  std_ulogic;
 
+      tick_i : in std_ulogic;
+      
       cmd_valid_i : in  std_ulogic;
       cmd_ready_o : out std_ulogic;
       cmd_data_i  : in  dp_cmd_data;