mii/rgmii: Allow to put delay on data rather than clock

Author: nipo

lib/nsl_mii/rgmii/gmii_to_rgmii.vhd

@@ -10,7 +10,8 @@ use nsl_io.diff.all;
 
 entity gmii_to_rgmii is
   generic(
-    clock_delay_ps_c: natural := 0
+    clock_delay_ps_c: natural := 0;
+    data_delay_ps_c: natural := 0
     );
   port(
     gmii_clk_i : in std_ulogic;
@@ -24,6 +25,7 @@ architecture beh of gmii_to_rgmii is
 
   signal ddr_io_txd  : std_ulogic_vector(11 downto 0);
   signal rgmii_group : work.rgmii.rgmii_io_group_t;
+  signal data_ddr_s: std_ulogic_vector(4 downto 0);
 
 begin
 
@@ -41,11 +43,22 @@ begin
     port map(
       clock_i          => to_diff(gmii_clk_i),
       d_i              => ddr_io_txd,
-      dd_o(3 downto 0) => rgmii_group.d,
-      dd_o(4)          => rgmii_group.ctl,
+      dd_o(4 downto 0) => data_ddr_s,
       dd_o(5)          => rgmii_group.c
       );
 
+  data_delay: nsl_io.delay.output_bus_delay_fixed
+    generic map(
+      width_c => 5,
+      delay_ps_c => data_delay_ps_c,
+      is_ddr_c => true
+      )
+    port map(
+      data_i => data_ddr_s,
+      data_o(0)      => rgmii_group.ctl,
+      data_o(1 to 4) => rgmii_group.d
+    );
+
   clock_delay: nsl_io.delay.output_delay_fixed
     generic map(
       delay_ps_c => clock_delay_ps_c

lib/nsl_mii/rgmii/rgmii.pkg.vhd

@@ -123,7 +123,8 @@ package rgmii is
 
   component gmii_to_rgmii is
     generic(
-      clock_delay_ps_c: natural := 0
+      clock_delay_ps_c: natural := 0;
+      data_delay_ps_c: natural := 0
       );
     port(
       gmii_clk_i : in std_ulogic;
@@ -135,7 +136,8 @@ package rgmii is
 
   component rgmii_to_gmii is
     generic(
-      clock_delay_ps_c: natural := 0
+      clock_delay_ps_c: natural := 0;
+      data_delay_ps_c: natural := 0
       );
     port(
       rgmii_i : in  rgmii_io_group_t;

lib/nsl_mii/rgmii/rgmii_to_gmii.vhd

@@ -10,7 +10,8 @@ use nsl_io.diff.all;
 
 entity rgmii_to_gmii is
   generic(
-    clock_delay_ps_c: natural := 0
+    clock_delay_ps_c: natural := 0;
+    data_delay_ps_c: natural := 0
     );
   port(
     rgmii_i : in  work.rgmii.rgmii_io_group_t;
@@ -26,6 +27,7 @@ architecture beh of rgmii_to_gmii is
   signal gmii_s : work.gmii.gmii_io_group_t;
   signal clock_s : std_ulogic;
   signal diff_clock_s : diff_pair;
+  signal data_delayed_s: std_ulogic_vector(4 downto 0);
 
 begin
 
@@ -47,15 +49,27 @@ begin
       );
 
   diff_clock_s <= swap(to_diff(clock_s));
+
+  data_delay: nsl_io.delay.input_bus_delay_fixed
+    generic map(
+      width_c => 5,
+      delay_ps_c => data_delay_ps_c,
+      is_ddr_c => true
+      )
+    port map(
+      data_i(0)      => rgmii_s.ctl,
+      data_i(1 to 4) => rgmii_s.d,
+      data_o => data_delayed_s
+    );
 
+
   ddr_input: nsl_io.ddr.ddr_bus_input
     generic map(
       ddr_width => 5
       )
     port map(
       clock_i          => diff_clock_s,
-      dd_i(3 downto 0) => rgmii_s.d,
-      dd_i(4)          => rgmii_s.ctl,
+      dd_i             => data_delayed_s,
       d_o(3 downto 0)  => gmii_s.data(3 downto 0),
       d_o(4)           => gmii_s.en,
       d_o(8 downto 5)  => gmii_s.data(7 downto 4),