drm/radeon: fix ordering in pll picking on dce4+

alexdeucher · alexdeucher · commit ecd67955fd4c · 2012-08-13T10:50:53.000-04:00
No functional change, but re-order the cases so they
evaluate properly due to the way the DCE macros work.

Noticed by kallisti5 on IRC.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 				 * crtc virtual pixel clock.
 				 */
 				if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
-					if (ASIC_IS_DCE5(rdev))
-						return ATOM_DCPLL;
+					if (rdev->clock.dp_extclk)
+						return ATOM_PPLL_INVALID;
 					else if (ASIC_IS_DCE6(rdev))
 						return ATOM_PPLL0;
-					else if (rdev->clock.dp_extclk)
-						return ATOM_PPLL_INVALID;
+					else if (ASIC_IS_DCE5(rdev))
+						return ATOM_DCPLL;
 				}
 			}
 		}

Original file line number	Diff line number	Diff line change
`@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)`
`1531`	`1531`	`* crtc virtual pixel clock.`
`1532`	`1532`	`*/`
`1533`	`1533`	`if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {`
`1534`		`- if (ASIC_IS_DCE5(rdev))`
`1535`		`- return ATOM_DCPLL;`
	`1534`	`+ if (rdev->clock.dp_extclk)`
	`1535`	`+ return ATOM_PPLL_INVALID;`
`1536`	`1536`	`else if (ASIC_IS_DCE6(rdev))`
`1537`	`1537`	`return ATOM_PPLL0;`
`1538`		`- else if (rdev->clock.dp_extclk)`
`1539`		`- return ATOM_PPLL_INVALID;`
	`1538`	`+ else if (ASIC_IS_DCE5(rdev))`
	`1539`	`+ return ATOM_DCPLL;`
`1540`	`1540`	`}`
`1541`	`1541`	`}`
`1542`	`1542`	`}`