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Merge branch 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Alex Deucher writes: This is the current set of radeon fixes for 3.6. Nothing too major. Highlights: - various display fixes - some SI fixes - new SI pci ids - major VM fix - CS checker support for MSAA I've tested on a number of cards across generations and noticed no problems. * 'drm-fixes-3.6' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: fix typo in function header comment drm/radeon/kms: implement timestamp userspace query (v2) drm/radeon/kms: add MSAA texture support for r600-evergreen drm/radeon/kms: reorder code in r600_check_texture_resource drm/radeon: fence virtual address and free it once idle v4 drm/radeon: fix some missing parens in asic macros drm/radeon: add some new SI pci ids drm/radeon: fix ordering in pll picking on dce4+ drm/radeon: do not reenable crtc after moving vram start address drm/radeon: fix bank tiling parameters on cayman drm/radeon: fix bank tiling parameters on evergreen drm/radeon: fix bank tiling parameters on SI drm/radeon: properly handle crtc powergating drm/radeon: properly handle SS overrides on TN (v2) drm/radeon/dce4+: set a more reasonable cursor watermark drm/radeon: fix handling for ddc type 5 on combios
2 parents 9830605 + f59abbf commit 7bac6b4

26 files changed

+320
-188
lines changed

‎drivers/gpu/drm/radeon/atombios_crtc.c

Lines changed: 16 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
259259
/* adjust pm to dpms changes BEFORE enabling crtcs */
260260
radeon_pm_compute_clocks(rdev);
261261
/* disable crtc pair power gating before programming */
262-
if (ASIC_IS_DCE6(rdev))
262+
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
263263
atombios_powergate_crtc(crtc, ATOM_DISABLE);
264264
atombios_enable_crtc(crtc, ATOM_ENABLE);
265265
if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
@@ -279,7 +279,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
279279
atombios_enable_crtc(crtc, ATOM_DISABLE);
280280
radeon_crtc->enabled = false;
281281
/* power gating is per-pair */
282-
if (ASIC_IS_DCE6(rdev)) {
282+
if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {
283283
struct drm_crtc *other_crtc;
284284
struct radeon_crtc *other_radeon_crtc;
285285
list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
@@ -1531,12 +1531,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
15311531
* crtc virtual pixel clock.
15321532
*/
15331533
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1534-
if (ASIC_IS_DCE5(rdev))
1535-
return ATOM_DCPLL;
1534+
if (rdev->clock.dp_extclk)
1535+
return ATOM_PPLL_INVALID;
15361536
else if (ASIC_IS_DCE6(rdev))
15371537
return ATOM_PPLL0;
1538-
else if (rdev->clock.dp_extclk)
1539-
return ATOM_PPLL_INVALID;
1538+
else if (ASIC_IS_DCE5(rdev))
1539+
return ATOM_DCPLL;
15401540
}
15411541
}
15421542
}
@@ -1635,18 +1635,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
16351635
static void atombios_crtc_prepare(struct drm_crtc *crtc)
16361636
{
16371637
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1638+
struct drm_device *dev = crtc->dev;
1639+
struct radeon_device *rdev = dev->dev_private;
16381640

1641+
radeon_crtc->in_mode_set = true;
16391642
/* pick pll */
16401643
radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
16411644

1645+
/* disable crtc pair power gating before programming */
1646+
if (ASIC_IS_DCE6(rdev))
1647+
atombios_powergate_crtc(crtc, ATOM_DISABLE);
1648+
16421649
atombios_lock_crtc(crtc, ATOM_ENABLE);
16431650
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
16441651
}
16451652

16461653
static void atombios_crtc_commit(struct drm_crtc *crtc)
16471654
{
1655+
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1656+
16481657
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
16491658
atombios_lock_crtc(crtc, ATOM_DISABLE);
1659+
radeon_crtc->in_mode_set = false;
16501660
}
16511661

16521662
static void atombios_crtc_disable(struct drm_crtc *crtc)

‎drivers/gpu/drm/radeon/evergreen.c

Lines changed: 11 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1229,24 +1229,8 @@ void evergreen_agp_enable(struct radeon_device *rdev)
12291229

12301230
void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
12311231
{
1232-
save->vga_control[0] = RREG32(D1VGA_CONTROL);
1233-
save->vga_control[1] = RREG32(D2VGA_CONTROL);
12341232
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
12351233
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1236-
save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1237-
save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1238-
if (rdev->num_crtc >= 4) {
1239-
save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1240-
save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1241-
save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1242-
save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1243-
}
1244-
if (rdev->num_crtc >= 6) {
1245-
save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1246-
save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1247-
save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1248-
save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1249-
}
12501234

12511235
/* Stop all video */
12521236
WREG32(VGA_RENDER_CONTROL, 0);
@@ -1357,47 +1341,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
13571341
/* Unlock host access */
13581342
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
13591343
mdelay(1);
1360-
/* Restore video state */
1361-
WREG32(D1VGA_CONTROL, save->vga_control[0]);
1362-
WREG32(D2VGA_CONTROL, save->vga_control[1]);
1363-
if (rdev->num_crtc >= 4) {
1364-
WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1365-
WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1366-
}
1367-
if (rdev->num_crtc >= 6) {
1368-
WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1369-
WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1370-
}
1371-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1372-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1373-
if (rdev->num_crtc >= 4) {
1374-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1375-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1376-
}
1377-
if (rdev->num_crtc >= 6) {
1378-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1379-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1380-
}
1381-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1382-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1383-
if (rdev->num_crtc >= 4) {
1384-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1385-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1386-
}
1387-
if (rdev->num_crtc >= 6) {
1388-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1389-
WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1390-
}
1391-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1392-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1393-
if (rdev->num_crtc >= 4) {
1394-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1395-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1396-
}
1397-
if (rdev->num_crtc >= 6) {
1398-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1399-
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1400-
}
14011344
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
14021345
}
14031346

@@ -1986,10 +1929,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
19861929
if (rdev->flags & RADEON_IS_IGP)
19871930
rdev->config.evergreen.tile_config |= 1 << 4;
19881931
else {
1989-
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1990-
rdev->config.evergreen.tile_config |= 1 << 4;
1991-
else
1932+
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1933+
case 0: /* four banks */
19921934
rdev->config.evergreen.tile_config |= 0 << 4;
1935+
break;
1936+
case 1: /* eight banks */
1937+
rdev->config.evergreen.tile_config |= 1 << 4;
1938+
break;
1939+
case 2: /* sixteen banks */
1940+
default:
1941+
rdev->config.evergreen.tile_config |= 2 << 4;
1942+
break;
1943+
}
19931944
}
19941945
rdev->config.evergreen.tile_config |= 0 << 8;
19951946
rdev->config.evergreen.tile_config |=

‎drivers/gpu/drm/radeon/evergreen_cs.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -788,6 +788,13 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
788788
case V_030000_SQ_TEX_DIM_1D_ARRAY:
789789
case V_030000_SQ_TEX_DIM_2D_ARRAY:
790790
depth = 1;
791+
break;
792+
case V_030000_SQ_TEX_DIM_2D_MSAA:
793+
case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
794+
surf.nsamples = 1 << llevel;
795+
llevel = 0;
796+
depth = 1;
797+
break;
791798
case V_030000_SQ_TEX_DIM_3D:
792799
break;
793800
default:

‎drivers/gpu/drm/radeon/ni.c

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -574,10 +574,18 @@ static void cayman_gpu_init(struct radeon_device *rdev)
574574
if (rdev->flags & RADEON_IS_IGP)
575575
rdev->config.cayman.tile_config |= 1 << 4;
576576
else {
577-
if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
578-
rdev->config.cayman.tile_config |= 1 << 4;
579-
else
577+
switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
578+
case 0: /* four banks */
580579
rdev->config.cayman.tile_config |= 0 << 4;
580+
break;
581+
case 1: /* eight banks */
582+
rdev->config.cayman.tile_config |= 1 << 4;
583+
break;
584+
case 2: /* sixteen banks */
585+
default:
586+
rdev->config.cayman.tile_config |= 2 << 4;
587+
break;
588+
}
581589
}
582590
rdev->config.cayman.tile_config |=
583591
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;

‎drivers/gpu/drm/radeon/r600.c

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3789,3 +3789,23 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
37893789
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
37903790
}
37913791
}
3792+
3793+
/**
3794+
* r600_get_gpu_clock - return GPU clock counter snapshot
3795+
*
3796+
* @rdev: radeon_device pointer
3797+
*
3798+
* Fetches a GPU clock counter snapshot (R6xx-cayman).
3799+
* Returns the 64 bit clock counter snapshot.
3800+
*/
3801+
uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
3802+
{
3803+
uint64_t clock;
3804+
3805+
mutex_lock(&rdev->gpu_clock_mutex);
3806+
WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3807+
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
3808+
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3809+
mutex_unlock(&rdev->gpu_clock_mutex);
3810+
return clock;
3811+
}

‎drivers/gpu/drm/radeon/r600_cs.c

Lines changed: 32 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1559,13 +1559,14 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
15591559
u32 tiling_flags)
15601560
{
15611561
struct r600_cs_track *track = p->track;
1562-
u32 nfaces, llevel, blevel, w0, h0, d0;
1563-
u32 word0, word1, l0_size, mipmap_size, word2, word3;
1562+
u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1563+
u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
15641564
u32 height_align, pitch, pitch_align, depth_align;
1565-
u32 array, barray, larray;
1565+
u32 barray, larray;
15661566
u64 base_align;
15671567
struct array_mode_checker array_check;
15681568
u32 format;
1569+
bool is_array;
15691570

15701571
/* on legacy kernel we don't perform advanced check */
15711572
if (p->rdev == NULL)
@@ -1583,12 +1584,28 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
15831584
word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
15841585
}
15851586
word1 = radeon_get_ib_value(p, idx + 1);
1587+
word2 = radeon_get_ib_value(p, idx + 2) << 8;
1588+
word3 = radeon_get_ib_value(p, idx + 3) << 8;
1589+
word4 = radeon_get_ib_value(p, idx + 4);
1590+
word5 = radeon_get_ib_value(p, idx + 5);
1591+
dim = G_038000_DIM(word0);
15861592
w0 = G_038000_TEX_WIDTH(word0) + 1;
1593+
pitch = (G_038000_PITCH(word0) + 1) * 8;
15871594
h0 = G_038004_TEX_HEIGHT(word1) + 1;
15881595
d0 = G_038004_TEX_DEPTH(word1);
1596+
format = G_038004_DATA_FORMAT(word1);
1597+
blevel = G_038010_BASE_LEVEL(word4);
1598+
llevel = G_038014_LAST_LEVEL(word5);
1599+
/* pitch in texels */
1600+
array_check.array_mode = G_038000_TILE_MODE(word0);
1601+
array_check.group_size = track->group_size;
1602+
array_check.nbanks = track->nbanks;
1603+
array_check.npipes = track->npipes;
1604+
array_check.nsamples = 1;
1605+
array_check.blocksize = r600_fmt_get_blocksize(format);
15891606
nfaces = 1;
1590-
array = 0;
1591-
switch (G_038000_DIM(word0)) {
1607+
is_array = false;
1608+
switch (dim) {
15921609
case V_038000_SQ_TEX_DIM_1D:
15931610
case V_038000_SQ_TEX_DIM_2D:
15941611
case V_038000_SQ_TEX_DIM_3D:
@@ -1601,29 +1618,25 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
16011618
break;
16021619
case V_038000_SQ_TEX_DIM_1D_ARRAY:
16031620
case V_038000_SQ_TEX_DIM_2D_ARRAY:
1604-
array = 1;
1621+
is_array = true;
16051622
break;
1606-
case V_038000_SQ_TEX_DIM_2D_MSAA:
16071623
case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1624+
is_array = true;
1625+
/* fall through */
1626+
case V_038000_SQ_TEX_DIM_2D_MSAA:
1627+
array_check.nsamples = 1 << llevel;
1628+
llevel = 0;
1629+
break;
16081630
default:
16091631
dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
16101632
return -EINVAL;
16111633
}
1612-
format = G_038004_DATA_FORMAT(word1);
16131634
if (!r600_fmt_is_valid_texture(format, p->family)) {
16141635
dev_warn(p->dev, "%s:%d texture invalid format %d\n",
16151636
__func__, __LINE__, format);
16161637
return -EINVAL;
16171638
}
16181639

1619-
/* pitch in texels */
1620-
pitch = (G_038000_PITCH(word0) + 1) * 8;
1621-
array_check.array_mode = G_038000_TILE_MODE(word0);
1622-
array_check.group_size = track->group_size;
1623-
array_check.nbanks = track->nbanks;
1624-
array_check.npipes = track->npipes;
1625-
array_check.nsamples = 1;
1626-
array_check.blocksize = r600_fmt_get_blocksize(format);
16271640
if (r600_get_array_mode_alignment(&array_check,
16281641
&pitch_align, &height_align, &depth_align, &base_align)) {
16291642
dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
@@ -1649,20 +1662,13 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
16491662
return -EINVAL;
16501663
}
16511664

1652-
word2 = radeon_get_ib_value(p, idx + 2) << 8;
1653-
word3 = radeon_get_ib_value(p, idx + 3) << 8;
1654-
1655-
word0 = radeon_get_ib_value(p, idx + 4);
1656-
word1 = radeon_get_ib_value(p, idx + 5);
1657-
blevel = G_038010_BASE_LEVEL(word0);
1658-
llevel = G_038014_LAST_LEVEL(word1);
16591665
if (blevel > llevel) {
16601666
dev_warn(p->dev, "texture blevel %d > llevel %d\n",
16611667
blevel, llevel);
16621668
}
1663-
if (array == 1) {
1664-
barray = G_038014_BASE_ARRAY(word1);
1665-
larray = G_038014_LAST_ARRAY(word1);
1669+
if (is_array) {
1670+
barray = G_038014_BASE_ARRAY(word5);
1671+
larray = G_038014_LAST_ARRAY(word5);
16661672

16671673
nfaces = larray - barray + 1;
16681674
}
@@ -1679,7 +1685,6 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
16791685
return -EINVAL;
16801686
}
16811687
/* using get ib will give us the offset into the mipmap bo */
1682-
word3 = radeon_get_ib_value(p, idx + 3) << 8;
16831688
if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
16841689
/*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
16851690
w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/

‎drivers/gpu/drm/radeon/r600d.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -602,6 +602,9 @@
602602
#define RLC_HB_WPTR 0x3f1c
603603
#define RLC_HB_WPTR_LSB_ADDR 0x3f14
604604
#define RLC_HB_WPTR_MSB_ADDR 0x3f18
605+
#define RLC_GPU_CLOCK_COUNT_LSB 0x3f38
606+
#define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c
607+
#define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40
605608
#define RLC_MC_CNTL 0x3f44
606609
#define RLC_UCODE_CNTL 0x3f48
607610
#define RLC_UCODE_ADDR 0x3f2c

‎drivers/gpu/drm/radeon/radeon.h

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -300,6 +300,7 @@ struct radeon_bo_va {
300300
uint64_t soffset;
301301
uint64_t eoffset;
302302
uint32_t flags;
303+
struct radeon_fence *fence;
303304
bool valid;
304305
};
305306

@@ -1533,6 +1534,7 @@ struct radeon_device {
15331534
unsigned debugfs_count;
15341535
/* virtual memory */
15351536
struct radeon_vm_manager vm_manager;
1537+
struct mutex gpu_clock_mutex;
15361538
};
15371539

15381540
int radeon_device_init(struct radeon_device *rdev,
@@ -1733,11 +1735,11 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
17331735
#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
17341736
#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
17351737
#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
1736-
#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1737-
#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1738-
#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1739-
#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->display.wait_for_vblank((rdev), (crtc))
1740-
#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1738+
#define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
1739+
#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
1740+
#define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
1741+
#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
1742+
#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
17411743

17421744
/* Common functions */
17431745
/* AGP */

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