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pwilkinJohannesGaessler
pwilkin
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JohannesGaessler
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Add support for CUMSUM and TRI for CUDA. (ggml-org#17584)
* Add support for CUMSUM and TRI for CUDA. * Minor optimizations. * Correct warp_prefix_inclusive_sum in float2 variant to return float2 * Optimize TRI * Whitespace * Fix strides. * Implement double loop * Whitespace * Fix HIP compilation bugs * Optimizations + big case performance tests * Implement using CUB with fallback to custom kernel * Remove error message. * Fixes from code review * Comment out CPU-unsupported F16/BF16 cases to fix CI * Fine, you win :P * Fix last cast, use NO_DEVICE_CODE and GGML_UNUSED_VARS * Vary warp-size based on physical warp size * Add GGML_UNUSED_VARS in tri as well * Use constexpr and call prefix_inclusive with warp_size template param * Update ggml/src/ggml-cuda/cumsum.cu Co-authored-by: Johannes Gäßler <johannesg@5d6.de> * Apply suggestions from code review Co-authored-by: Johannes Gäßler <johannesg@5d6.de> * Change to tid % warp_size * Fix strides; hardcode mask; add ggml_lane_mask_t * Missing renames, remove unused get_warp_mask(), explicit calls to ggml_cuda_info() * Too hasty... --------- Co-authored-by: Johannes Gäßler <johannesg@5d6.de>
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‎ggml/src/ggml-cuda/common.cuh‎

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Original file line numberDiff line numberDiff line change
@@ -463,6 +463,53 @@ static __device__ __forceinline__ float warp_reduce_max(float x) {
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return x;
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}
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template<typename T, int width = WARP_SIZE>
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static __device__ __forceinline__ T warp_prefix_inclusive_sum(T x) {
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const int lane_id = threadIdx.x % width;
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#pragma unroll
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for (int offset = 1; offset < width; offset <<= 1) {
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const T t = __shfl_up_sync(0xffffffff, x, offset, width);
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if (lane_id >= offset) {
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x += t;
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}
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}
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return x;
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}
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template<int width = WARP_SIZE>
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static __device__ __forceinline__ float2 warp_prefix_inclusive_sum(float2 a) {
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const int lane_id = threadIdx.x % width;
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#pragma unroll
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for (int offset = 1; offset < width; offset <<= 1) {
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const float t_x = __shfl_up_sync(0xffffffff, a.x, offset, width);
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const float t_y = __shfl_up_sync(0xffffffff, a.y, offset, width);
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if (lane_id >= offset) {
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a.x += t_x;
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a.y += t_y;
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}
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}
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return a;
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}
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template<int width = WARP_SIZE>
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static __device__ __forceinline__ half2 warp_prefix_inclusive_sum(half2 a) {
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#ifdef FP16_AVAILABLE
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const int lane_id = threadIdx.x % width;
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#pragma unroll
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for (int offset = 1; offset < width; offset <<= 1) {
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const half2 t = __shfl_up_sync(0xffffffff, a, offset, width);
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if (lane_id >= offset) {
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a = __hadd2(a, t);
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}
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}
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return a;
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#else
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NO_DEVICE_CODE;
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return a;
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#endif // FP16_AVAILABLE
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}
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static __device__ __forceinline__ half ggml_cuda_hmax(const half a, const half b) {
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#ifdef FP16_AVAILABLE
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‎ggml/src/ggml-cuda/cumsum.cu‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,237 @@
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#include <algorithm>
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#include "cumsum.cuh"
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#include "convert.cuh"
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#include "ggml-cuda/common.cuh"
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#include "ggml.h"
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#ifdef GGML_CUDA_USE_CUB
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# include <cub/device/device_scan.cuh>
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#endif // GGML_CUDA_USE_CUB
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template<typename T, int BLOCK_SIZE>
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static __global__ void cumsum_cub_kernel(
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const T * __restrict__ src,
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T * __restrict__ dst,
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const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03,
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const int64_t s01, const int64_t s02, const int64_t s03,
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const int64_t s1, const int64_t s2, const int64_t s3) {
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#ifdef GGML_CUDA_USE_CUB
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using BlockScan = cub::BlockScan<T, BLOCK_SIZE>;
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__shared__ typename BlockScan::TempStorage temp_storage;
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__shared__ T block_carry; // carry from previous tile
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const int tid = threadIdx.x;
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const int64_t i1 = blockIdx.x;
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const int64_t i2 = blockIdx.y;
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const int64_t i3 = blockIdx.z;
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if (i1 >= ne01 || i2 >= ne02 || i3 >= ne03) {
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return;
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}
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const T * src_row = src + i1 * s01 + i2 * s02 + i3 * s03;
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T * dst_row = dst + i1 * s1 + i2 * s2 + i3 * s3;
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if (tid == 0) {
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block_carry = 0;
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}
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__syncthreads();
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for (int64_t start = 0; start < ne00; start += BLOCK_SIZE) {
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int64_t idx = start + tid;
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T x = (idx < ne00) ? src_row[idx] : T(0);
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T inclusive;
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T block_total;
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BlockScan(temp_storage).InclusiveSum(x, inclusive, block_total);
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__syncthreads();
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T final_val = inclusive + block_carry;
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// store result
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if (idx < ne00) {
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dst_row[idx] = final_val;
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}
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__syncthreads();
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if (tid == 0) {
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block_carry += block_total;
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}
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__syncthreads();
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}
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#else
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NO_DEVICE_CODE;
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#endif // GGML_CUDA_USE_CUB
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}
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// Fallback kernel implementation (original)
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template<typename T>
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static __global__ void cumsum_kernel(
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const T * src, T * dst,
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const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03,
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const int64_t s00, const int64_t s01, const int64_t s02, const int64_t s03,
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const int64_t s0, const int64_t s1, const int64_t s2, const int64_t s3) {
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GGML_UNUSED_VARS(s00, s0);
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const int tid = threadIdx.x;
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constexpr int warp_size = ggml_cuda_get_physical_warp_size();
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const int lane = tid % warp_size;
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const int warp = tid / warp_size;
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const int warps_per_block = blockDim.x / warp_size;
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extern __shared__ float smem[];
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float * s_vals = smem;
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float * s_warp_sums = smem + blockDim.x;
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float * s_carry = smem + blockDim.x + warps_per_block;
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float * s_chunk_total = s_carry + 1;
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// Initialize carry
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if (tid == 0) {
96+
*s_carry = 0.0f;
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}
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__syncthreads();
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const int64_t i3 = blockIdx.z;
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const int64_t i2 = blockIdx.y;
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const int64_t i1 = blockIdx.x;
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if (i3 >= ne03 || i2 >= ne02 || i1 >= ne01) {
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return;
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}
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const T * src_row = src + i1 * s01 + i2 * s02 + i3 * s03;
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T * dst_row = dst + i1 * s1 + i2 * s2 + i3 * s3;
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for (int64_t start = 0; start < ne00; start += blockDim.x) {
111+
int64_t idx = start + tid;
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float val = (idx < ne00) ? ggml_cuda_cast<float, T>(src_row[idx]) : 0.0f;
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// 1. Warp inclusive scan
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val = warp_prefix_inclusive_sum<T, warp_size>(val);
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s_vals[tid] = val;
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// Store warp total
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if (lane == warp_size - 1) {
120+
s_warp_sums[warp] = val;
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}
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__syncthreads();
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// 2. Exclusive scan of warp sums (warp 0 only)
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if (warp == 0) {
126+
float w = (tid < warps_per_block) ? s_warp_sums[tid] : 0.0f;
127+
float inc = warp_prefix_inclusive_sum<T, warp_size>(w);
128+
if (tid < warps_per_block) {
129+
s_warp_sums[tid] = inc - w; // exclusive sum
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}
131+
if (tid == warps_per_block - 1) {
132+
*s_chunk_total = inc; // total sum of this chunk
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}
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}
135+
__syncthreads();
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137+
float carry = *s_carry;
138+
float final_val = s_vals[tid] + s_warp_sums[warp] + carry;
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if (idx < ne00) {
140+
dst_row[idx] = ggml_cuda_cast<T, float>(final_val);
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}
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__syncthreads();
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// Update carry for next chunk
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if (tid == 0) {
146+
*s_carry += *s_chunk_total;
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}
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__syncthreads();
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}
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}
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template<typename T>
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static void cumsum_cuda(
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const T * src, T * dst,
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const int64_t ne00, const int64_t ne01, const int64_t ne02, const int64_t ne03,
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const int64_t nb00, const int64_t nb01, const int64_t nb02, const int64_t nb03,
157+
const int64_t nb0, const int64_t nb1, const int64_t nb2, const int64_t nb3,
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cudaStream_t stream) {
159+
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const size_t type_size = sizeof(T);
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bool use_cub = false;
162+
#ifdef GGML_CUDA_USE_CUB
163+
// Check if we can use CUB (data must be contiguous along innermost dimension)
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const bool is_contiguous = (nb00 == type_size) && (nb0 == type_size);
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if (is_contiguous) {
167+
use_cub = true;
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}
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#endif // GGML_CUDA_USE_CUB
170+
dim3 grid_dims(ne01, ne02, ne03);
171+
const auto &info = ggml_cuda_info().devices[ggml_cuda_get_device()];
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const int warp_size = info.warp_size;
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const int num_warps = (ne00 + warp_size - 1) / warp_size;
174+
int block_size = num_warps * warp_size;
175+
block_size = std::min(block_size, CUDA_CUMSUM_BLOCK_SIZE);
176+
dim3 block_dims(block_size, 1, 1);
177+
const int warps_per_block = block_size / warp_size;
178+
const size_t shmem_size = (block_size + warps_per_block + 2) * sizeof(float);
179+
180+
if (use_cub) {
181+
cumsum_cub_kernel<T, CUDA_CUMSUM_BLOCK_SIZE><<<grid_dims, CUDA_CUMSUM_BLOCK_SIZE, 0, stream>>>(
182+
src, dst,
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ne00, ne01, ne02, ne03,
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nb01 / type_size, nb02 / type_size, nb03 / type_size,
185+
nb1 / type_size, nb2 / type_size, nb3 / type_size
186+
);
187+
} else {
188+
cumsum_kernel<<<grid_dims, block_dims, shmem_size, stream>>>(
189+
src, dst,
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ne00, ne01, ne02, ne03,
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nb00 / type_size, nb01 / type_size, nb02 / type_size, nb03 / type_size,
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nb0 / type_size, nb1 / type_size, nb2 / type_size, nb3 / type_size
193+
);
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}
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}
196+
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void ggml_cuda_op_cumsum(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
198+
const ggml_tensor * src0 = dst->src[0];
199+
cudaStream_t stream = ctx.stream();
200+
201+
GGML_ASSERT(src0->type == dst->type);
202+
switch(src0->type) {
203+
case GGML_TYPE_F32:
204+
{
205+
cumsum_cuda(
206+
(const float *)src0->data, (float *)dst->data,
207+
src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3],
208+
src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3],
209+
dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3],
210+
stream
211+
);
212+
} break;
213+
// We do not support those on CPU for now anyway, so comment them out because they cause errors on some CI platforms
214+
/*case GGML_TYPE_F16:
215+
{
216+
cumsum_cuda(
217+
(const half *)src0->data, (half *)dst->data,
218+
src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3],
219+
src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3],
220+
dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3],
221+
stream
222+
);
223+
} break;
224+
case GGML_TYPE_BF16:
225+
{
226+
cumsum_cuda(
227+
(const nv_bfloat16 *)src0->data, (nv_bfloat16 *)dst->data,
228+
src0->ne[0], src0->ne[1], src0->ne[2], src0->ne[3],
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src0->nb[0], src0->nb[1], src0->nb[2], src0->nb[3],
230+
dst->nb[0], dst->nb[1], dst->nb[2], dst->nb[3],
231+
stream
232+
);
233+
} break;*/
234+
default:
235+
GGML_ABORT("fatal error");
236+
}
237+
}

‎ggml/src/ggml-cuda/cumsum.cuh‎

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@@ -0,0 +1,5 @@
1+
#include "common.cuh"
2+
3+
#define CUDA_CUMSUM_BLOCK_SIZE 256
4+
5+
void ggml_cuda_op_cumsum(ggml_backend_cuda_context & ctx, ggml_tensor * dst);

‎ggml/src/ggml-cuda/ggml-cuda.cu‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,8 @@
5454
#include "ggml-cuda/set-rows.cuh"
5555
#include "ggml-cuda/pad_reflect_1d.cuh"
5656
#include "ggml-cuda/solve_tri.cuh"
57+
#include "ggml-cuda/tri.cuh"
58+
#include "ggml-cuda/cumsum.cuh"
5759
#include "ggml.h"
5860

5961
#include <algorithm>
@@ -2701,6 +2703,12 @@ static bool ggml_cuda_compute_forward(ggml_backend_cuda_context & ctx, struct gg
27012703
case GGML_OP_CROSS_ENTROPY_LOSS:
27022704
ggml_cuda_cross_entropy_loss(ctx, dst);
27032705
break;
2706+
case GGML_OP_CUMSUM:
2707+
ggml_cuda_op_cumsum(ctx, dst);
2708+
break;
2709+
case GGML_OP_TRI:
2710+
ggml_cuda_op_tri(ctx, dst);
2711+
break;
27042712
case GGML_OP_RWKV_WKV6:
27052713
ggml_cuda_op_rwkv_wkv6(ctx, dst);
27062714
break;
@@ -4609,6 +4617,8 @@ static bool ggml_backend_cuda_device_supports_op(ggml_backend_dev_t dev, const g
46094617
case GGML_OP_CROSS_ENTROPY_LOSS_BACK:
46104618
case GGML_OP_OPT_STEP_ADAMW:
46114619
case GGML_OP_OPT_STEP_SGD:
4620+
case GGML_OP_CUMSUM:
4621+
case GGML_OP_TRI:
46124622
return true;
46134623
case GGML_OP_SOLVE_TRI:
46144624
return op->src[0]->ne[0] <= 64 && op->src[1]->ne[0] <= 32;

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