diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x410.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x410.xml deleted file mode 100644 index 460b862e..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x410.xml +++ /dev/null @@ -1,475 +0,0 @@ - - - - 0x410 - STMicroelectronics - MCU - Cortex-M3 - STM32F101/F102/F103 Medium-density - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x411.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x411.xml deleted file mode 100644 index 990b13c7..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x411.xml +++ /dev/null @@ -1,406 +0,0 @@ - - - - 0x411 - STMicroelectronics - MCU - Cortex-M3 - STM32F2xx - STM32F2 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x412.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x412.xml deleted file mode 100644 index 5aca7572..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x412.xml +++ /dev/null @@ -1,399 +0,0 @@ - - - - 0x412 - STMicroelectronics - MCU - Cortex-M3 - STM32F101/F102/F103 Low-density - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x413.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x413.xml deleted file mode 100644 index a6e2f0e0..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x413.xml +++ /dev/null @@ -1,322 +0,0 @@ - - - - 0x413 - STMicroelectronics - MCU - Cortex-M4 - STM32F405xx/F407xx/F415xx/F417xx - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x414.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x414.xml deleted file mode 100644 index 97558cd2..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x414.xml +++ /dev/null @@ -1,475 +0,0 @@ - - - - 0x414 - STMicroelectronics - MCU - Cortex-M3 - STM32F101/F103 High-density - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x415.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x415.xml deleted file mode 100644 index 6c667ba6..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x415.xml +++ /dev/null @@ -1,932 +0,0 @@ - - - - 0x415 - STMicroelectronics - MCU - Cortex-M4 - STM32L4x1/STM32L475xx/STM32L476xx/STM32L486xx - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DualBank - - 0x15 - 0x1 - RW - - 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 - 256 KB/512 KB Dual-bank Flash - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DualBank - - 0x15 - 0x1 - RW - - 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 - 256 KB/512 KB Dual-bank Flash - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x416.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x416.xml deleted file mode 100644 index 602a7725..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x416.xml +++ /dev/null @@ -1,484 +0,0 @@ - - - - 0x416 - STMicroelectronics - MCU - Cortex-M3 - STM32L100x8/STM32L100xB/STM32L15xx6/STM32L15xx8/STM32L15xxB - STM32L1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x417.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x417.xml deleted file mode 100644 index 4c188438..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x417.xml +++ /dev/null @@ -1,576 +0,0 @@ - - - - 0x417 - STMicroelectronics - MCU - Cortex-M0+ - STM32L05x/L06x/L010 - STM32L0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x1F - 0x1 - R - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - - Write Protection - - - - - WRPOT1 - - 0x0 - 0x10 - R - - Write protection not active - Write protection active - - - - WRPOT1 - - 0x0 - 0x10 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x0F - 0x1 - W - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT1 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x0F - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT1 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x418.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x418.xml deleted file mode 100644 index 29c0199c..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x418.xml +++ /dev/null @@ -1,475 +0,0 @@ - - - - 0x418 - STMicroelectronics - MCU - Cortex-M3 - STM32F105/F107 Connectivity Line - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x419.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x419.xml deleted file mode 100644 index c2ceb99b..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x419.xml +++ /dev/null @@ -1,599 +0,0 @@ - - - - 0x419 - STMicroelectronics - MCU - Cortex-M4 - STM32F42xxx/F43xxx - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - BFB2 - - 0x4 - 0x1 - RW - - Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) - Dual-bank boot enabled. Boot is always performed from system memory. - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - DB1M - Dual-bank on 1 Mbyte Flash memory devices - 0x1E - 0x1 - RW - - 1 Mbyte single bank Flash memory (contiguous addresses in bank1) - 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each - - - - - - - Write Protection - - - - - nWRP0 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP0 - - 0x10 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - nWRP12 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP12 - - 0x10 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - BFB2 - - 0x4 - 0x1 - RW - - Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) - Dual-bank boot enabled. Boot is always performed from system memory. - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - DB1M - Dual-bank on 1 Mbyte Flash memory devices - 0x1E - 0x1 - RW - - 1 Mbyte single bank Flash memory (contiguous addresses in bank1) - 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each - - - - - - - Write Protection (Bank 1) - - - - - WRP0 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Write Protection (Bank 2) - - - - - WRP12 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - WRP12 - - 0x0 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x420.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x420.xml deleted file mode 100644 index dbf082ef..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x420.xml +++ /dev/null @@ -1,475 +0,0 @@ - - - - 0x420 - STMicroelectronics - MCU - Cortex-M3 - STM32F100 Low/Medium density Value Line - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x421.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x421.xml deleted file mode 100644 index 44e672f8..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x421.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x421 - STMicroelectronics - MCU - Cortex-M4 - STM32F446xx - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x422.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x422.xml deleted file mode 100644 index 295fd937..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x422.xml +++ /dev/null @@ -1,244 +0,0 @@ - - - - 0x422 - STMicroelectronics - MCU - Cortex-M4 - STM32F302xB-xC/STM32F303xB-xC/F358xx - STM32F3 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - SRAM_PE - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x423.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x423.xml deleted file mode 100644 index ce444ee6..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x423.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x423 - STMicroelectronics - MCU - Cortex-M4 - STM32F401xB/C - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0x6 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0x6 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x6 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0x6 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x425.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x425.xml deleted file mode 100644 index 3ac1f747..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x425.xml +++ /dev/null @@ -1,567 +0,0 @@ - - - - 0x425 - STMicroelectronics - MCU - Cortex-M0+ - STM32L03x/L04x/L010 - STM32L0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x1F - 0x1 - R - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x8 - R - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x8 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x0F - 0x1 - W - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x8 - W - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - - 0x0F - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x8 - RW - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x8 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x427.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x427.xml deleted file mode 100644 index 94733176..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x427.xml +++ /dev/null @@ -1,753 +0,0 @@ - - - - 0x427 - STMicroelectronics - MCU - Cortex-M3 - STM32L100xC/STM32L15xxC/STM32L162xC - STM32L1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - WRP32 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - WRP32 - - 0x0 - 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP32 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - WRP48 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP48 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP32 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - WRP48 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP48 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x428.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x428.xml deleted file mode 100644 index bdb7ef40..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x428.xml +++ /dev/null @@ -1,475 +0,0 @@ - - - - 0x428 - STMicroelectronics - MCU - Cortex-M3 - STM32F100 High-density Value Line - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x429.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x429.xml deleted file mode 100644 index 4a11fef4..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x429.xml +++ /dev/null @@ -1,618 +0,0 @@ - - - - 0x429 - STMicroelectronics - MCU - Cortex-M3 - STM32L100x6xxA/STM32L100x8xxA/STM32L100xBxxA/STM32L15xx6xxA/STM32L15xx8xxA/STM32L15xxBxxA - STM32L1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector write/read (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP0 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRP16 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x430.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x430.xml deleted file mode 100644 index 25b65c17..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x430.xml +++ /dev/null @@ -1,513 +0,0 @@ - - - - 0x430 - STMicroelectronics - MCU - Cortex-M3 - STM32F101/F103 XL-density - STM32F1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x1 - 0x1 - R - - Flash memory is not read-protected. - Flash memory is read-protected. - - - - - - - User Configuration - - - - - WDG_SW - - 0x2 - 0x1 - R - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x3 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x4 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x5 - 0x1 - R - - The device will boot from Flash memory bank 2 when boot pins are set in user Flash position - The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0xA - 0x8 - R - - - Data1 - User data 1 (8-bit) - 0x12 - 0x8 - R - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - W - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x13 - 0x1 - W - - The device will boot from Flash memory bank 2 when boot pins are set in user Flash position - The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - W - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - W - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x13 - 0x1 - RW - - The device will boot from Flash memory bank 2 when boot pins are set in user Flash position - The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - WRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - WRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x431.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x431.xml deleted file mode 100644 index acd7d2af..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x431.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x431 - STMicroelectronics - MCU - Cortex-M4 - STM32F411xC/E - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x432.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x432.xml deleted file mode 100644 index 8bfd22b1..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x432.xml +++ /dev/null @@ -1,255 +0,0 @@ - - - - 0x432 - STMicroelectronics - MCU - Cortex-M4 - STM32F37xx - STM32F3 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - SDADC12_VDD - - 0x17 - 0x1 - RW - - SDADC12_VDD power supply supervisor disabled. - SDADC12_VDD power supply supervisor enabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x433.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x433.xml deleted file mode 100644 index 6bdd4cb0..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x433.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x433 - STMicroelectronics - MCU - Cortex-M4 - STM32F401xD/E - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x8 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0x8 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x434.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x434.xml deleted file mode 100644 index a0386f30..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x434.xml +++ /dev/null @@ -1,599 +0,0 @@ - - - - 0x434 - STMicroelectronics - MCU - Cortex-M4 - STM32F469xx/F467xx - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - BFB2 - - 0x4 - 0x1 - RW - - Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) - Dual-bank boot enabled. Boot is always performed from system memory. - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - DB1M - Dual-bank on 1 Mbyte Flash memory devices - 0x1E - 0x1 - RW - - 1 Mbyte single bank Flash memory (contiguous addresses in bank1) - 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each - - - - - - - Write Protection - - - - - nWRP0 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP0 - - 0x10 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - nWRP12 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP12 - - 0x10 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - BFB2 - - 0x4 - 0x1 - RW - - Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) - Dual-bank boot enabled. Boot is always performed from system memory. - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - DB1M - Dual-bank on 1 Mbyte Flash memory devices - 0x1E - 0x1 - RW - - 1 Mbyte single bank Flash memory (contiguous addresses in bank1) - 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP0 - - 0x0 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Write Protection - - - - - nWRP12 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - nWRP12 - - 0x0 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x435.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x435.xml deleted file mode 100644 index 7d079912..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x435.xml +++ /dev/null @@ -1,654 +0,0 @@ - - - - 0x435 - STMicroelectronics - MCU - Cortex-M4 - STM32L43xxx/STM32L44xxx - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x436.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x436.xml deleted file mode 100644 index 0ce44164..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x436.xml +++ /dev/null @@ -1,692 +0,0 @@ - - - - 0x436 - STMicroelectronics - MCU - Cortex-M3 - STM32L15xxD/STM32L162xD - STM32L1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Dual - 0x4 - - - - - - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x17 - 0x1 - R - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - WRP64 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - W - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP48 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP64 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - WRP80 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - RW - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP48 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP64 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP80 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x437.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x437.xml deleted file mode 100644 index 3cc4bc09..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x437.xml +++ /dev/null @@ -1,647 +0,0 @@ - - - - 0x437 - STMicroelectronics - MCU - Cortex-M3 - STM32L15xxE/STM32L162xE - STM32L1 - ARM 32-bit Cortex-M3 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Dual - 0x4 - - - - - - - - - - - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Dual - 0x4 - - - - - - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x17 - 0x1 - R - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - WRP64 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - WRP96 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - W - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBFB2 - - 0x7 - 0x1 - RW - - If boot from Flash then boot from bank 2 - If boot from Flash then boot from bank 1 - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP32 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP48 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP64 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP80 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - - Write Protection - - - - - WRP96 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - WRP112 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x438.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x438.xml deleted file mode 100644 index 2b95abe6..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x438.xml +++ /dev/null @@ -1,217 +0,0 @@ - - - - 0x438 - STMicroelectronics - MCU - Cortex-M4 - STM32F303x4-x6-x8/F328xx/F334xx - STM32F3 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - SRAM_PE - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x439.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x439.xml deleted file mode 100644 index 10d31876..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x439.xml +++ /dev/null @@ -1,217 +0,0 @@ - - - - 0x439 - STMicroelectronics - MCU - Cortex-M4 - STM32F301x4-x6-x8/STM32F302x4-x6-x8/F318xx - STM32F3 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - SRAM_PE - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x440.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x440.xml deleted file mode 100644 index 64097588..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x440.xml +++ /dev/null @@ -1,217 +0,0 @@ - - - - 0x440 - STMicroelectronics - MCU - Cortex-M0 - STM32F05x/F030x8 - STM32F0 - ARM 32-bit Cortex-M0 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. - 0x14 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x441.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x441.xml deleted file mode 100644 index a70525e3..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x441.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x441 - STMicroelectronics - MCU - Cortex-M4 - STM32F412 - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0xC - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0xC - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0xC - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x442.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x442.xml deleted file mode 100644 index 705c5e26..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x442.xml +++ /dev/null @@ -1,266 +0,0 @@ - - - - 0x442 - STMicroelectronics - MCU - Cortex-M0 - STM32F09x/F030xC - STM32F0 - ARM 32-bit Cortex-M0 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x13 - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. - 0x14 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - BOOT_SEL - - 0x17 - 0x1 - RW - - BOOT0 signal is defined by nBOOT0 option bit - BOOT0 signal is defined by BOOT0 pin value - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x444.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x444.xml deleted file mode 100644 index 19c7f6e0..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x444.xml +++ /dev/null @@ -1,206 +0,0 @@ - - - - 0x444 - STMicroelectronics - MCU - Cortex-M0 - STM32F03x - STM32F0 - ARM 32-bit Cortex-M0 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x445.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x445.xml deleted file mode 100644 index 442c1c6b..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x445.xml +++ /dev/null @@ -1,228 +0,0 @@ - - - - 0x445 - STMicroelectronics - MCU - Cortex-M0 - STM32F04x/F070x6 - STM32F0 - ARM 32-bit Cortex-M0 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x13 - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - BOOT_SEL - - 0x17 - 0x1 - RW - - BOOT0 signal is defined by nBOOT0 option bit - BOOT0 signal is defined by BOOT0 pin value - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x446.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x446.xml deleted file mode 100644 index 4c563641..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x446.xml +++ /dev/null @@ -1,266 +0,0 @@ - - - - 0x446 - STMicroelectronics - MCU - Cortex-M4 - STM32F302xE/F303xE/F398xx - STM32F3 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT0 - - 0x13 - 0x1 - RW - - Main Flash memory is selected as boot area - nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from Embedded SRAM when BOOT0=1 - Boot from System flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - BOOT_SEL - - 0x17 - 0x1 - RW - - BOOT0 signal is defined by nBOOT0 option bit - BOOT0 signal is defined by BOOT0 pin value - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x447.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x447.xml deleted file mode 100644 index 863be2d2..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x447.xml +++ /dev/null @@ -1,829 +0,0 @@ - - - - 0x447 - STMicroelectronics - MCU - Cortex-M0+ - STM32L07x/L08x/L010 - STM32L0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x17 - 0x1 - R - - Boot from flash bank 1 - boot from flash bank 2 - - - - nBOOT1 - - 0x1F - 0x1 - R - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x20 - R - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x20 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - WRPOT32 - - 0x0 - 0x10 - R - - Write protection not active - Write protection active - - - - WRPOT32 - - 0x0 - 0x10 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x7 - 0x1 - W - - Boot from flash bank 1 - boot from flash bank 2 - - - - nBOOT1 - - 0x0F - 0x1 - W - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - WRPOT16 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRPOT16 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - WRPOT32 - - 0x0 - 0x10 - W - - Write protection not active - Write protection active - - - - WRPOT32 - - 0x0 - 0x10 - W - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - BFB2 - - 0x7 - 0x1 - RW - - Boot from flash bank 1 - boot from flash bank 2 - - - - nBOOT1 - - 0x0F - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - WRPOT16 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRPOT16 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - WRPOT32 - - 0x0 - 0x10 - RW - - Write protection not active - Write protection active - - - - WRPOT32 - - 0x0 - 0x10 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x448.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x448.xml deleted file mode 100644 index 9fbafb60..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x448.xml +++ /dev/null @@ -1,244 +0,0 @@ - - - - 0x448 - STMicroelectronics - MCU - Cortex-M0 - STM32F07x - STM32F0 - ARM 32-bit Cortex-M0 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - User Configuration - - - - - WDG_SW - - 0x10 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x11 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x12 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT1 - Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. - 0x14 - 0x1 - RW - - Boot from embedded SRAM when BOOT0=1 - Boot from system flash when BOOT0=1 - - - - VDDA_MONITOR - - 0x15 - 0x1 - RW - - VDDA power supply supervisor disabled - VDDA power supply supervisor enabled - - - - RAM_PARITY - - 0x16 - 0x1 - RW - - RAM parity check enabled - RAM parity check disabled - - - - - - - User Data - - - - - Data0 - User data 0 (8-bit) - 0x0 - 0x8 - RW - - - Data1 - User data 1 (8-bit) - 0x10 - 0x8 - RW - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP8 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP16 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP24 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x449.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x449.xml deleted file mode 100644 index fb0a7732..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x449.xml +++ /dev/null @@ -1,527 +0,0 @@ - - - - 0x449 - STMicroelectronics - MCU - Cortex-M7 - STM32F74x/STM32F75x - STM32F7 - ARM 32-bit Cortex-M7 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x10 - - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - ITCM Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x10 - - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x1F - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x1E - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x10 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x10 - 0x2 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0xF - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0xE - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - - - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x0 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x450.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x450.xml deleted file mode 100644 index 3f43cf90..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x450.xml +++ /dev/null @@ -1,1117 +0,0 @@ - - - - 0x450 - STMicroelectronics - MCU - Cortex-M7 - STM32H7xx - STM32H7 - ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x20 - - - - - - - - - - - - - - - - Single - 0x20 - - - - - - - - - - ITCM Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Dual - 0x20 - - - - - - - - - - - - - - - - Single - 0x20 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - RSS - - - - - RSS1 - - 0x1A - 0x1 - R - - No SFI process on going - SFI process started - - - - - - - - - RSS1 - - 0x1A - 0x1 - W - - No SFI process on going - SFI process started - - - - - - - BOR Level - - - - - BOR_LEV - These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. - 0x2 - 0x2 - R - - reset level is set to VBOR0 - reset level is set to VBOR1 - reset level is set to VBOR2 - reset level is set to VBOR3 - - - - - - - - - BOR_LEV - These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. - 0x2 - 0x2 - W - - reset level is set to VBOR0 - reset level is set to VBOR1 - reset level is set to VBOR2 - reset level is set to VBOR3 - - - - - - - User Configuration - - - - - IWDG1_SW - - 0x4 - 0x1 - R - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - IWDG2_SW - - 0x5 - 0x1 - R - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP_D1 - - 0x6 - 0x1 - R - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY_D1 - - 0x7 - 0x1 - R - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - FZ_IWDG_STOP - - 0x11 - 0x1 - R - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - FZ_IWDG_SDBY - - 0x12 - 0x1 - R - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - R - - Security feature disabled - Security feature enabled - - - - BCM4 - - 0x16 - 0x1 - R - - CM4 boot disabled - CM4 boot enabled - - - - BCM7 - - 0x17 - 0x1 - R - - CM7 boot disabled - CM7 boot enabled - - - - NRST_STOP_D2 - - 0x18 - 0x1 - R - - STOP mode on Domain 2 is entering with reset - STOP mode on Domain 2 is entering without reset - - - - NRST_STBY_D2 - - 0x19 - 0x1 - R - - STANDBY mode on Domain 2 is entering with reset - STANDBY mode on Domain 2 is entering without reset - - - - SWAP_BANK - - 0x1F - 0x1 - R - - after boot loading, no swap for user sectors - after boot loading, user sectors swapped - - - - IO_HSLV - I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V - 0x1D - 0x1 - R - - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - - - - - - IWDG1_SW - - 0x4 - 0x1 - W - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - IWDG2_SW - - 0x5 - 0x1 - W - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP_D1 - - 0x6 - 0x1 - W - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY_D1 - - 0x7 - 0x1 - W - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - FZ_IWDG_STOP - - 0x11 - 0x1 - W - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - FZ_IWDG_SDBY - - 0x12 - 0x1 - W - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - W - - Security feature disabled - Security feature enabled - - - - IO_HSLV - I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V - 0x1D - 0x1 - W - - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - BCM4 - - 0x16 - 0x1 - W - - CM4 boot disabled - CM4 boot enabled - - - - BCM7 - - 0x17 - 0x1 - W - - CM7 boot disabled - CM7 boot enabled - - - - NRST_STOP_D2 - - 0x18 - 0x1 - W - - STOP mode on Domain 2 is entering with reset - STOP mode on Domain 2 is entering without reset - - - - NRST_STBY_D2 - - 0x19 - 0x1 - W - - STANDBY mode on Domain 2 is entering with reset - STANDBY mode on Domain 2 is entering without reset - - - - SWAP_BANK - - 0x1F - 0x1 - W - - after boot loading, no swap for user sectors - after boot loading, user sectors swapped - - - - - - - Boot address Option Bytes - - - - - BOOT_CM7_ADD0 - Define the boot address for Cortex-M7 when BOOT0=0 - 0x0 - 0x10 - R - - - - BOOT_CM7_ADD1 - Define the boot address for Cortex-M7 when BOOT0=1 - 0x10 - 0x10 - R - - - - - - - - - BOOT_CM4_ADD0 - Define the boot address for Cortex-M4 when BOOT0=0 - 0x0 - 0x10 - R - - - - BOOT_CM4_ADD1 - Define the boot address for Cortex-M4 when BOOT0=1 - 0x10 - 0x10 - R - - - - - - - - - BOOT_CM7_ADD0 - - 0x0 - 0x10 - W - - - - BOOT_CM7_ADD1 - - 0x10 - 0x10 - W - - - - - - - - - BOOT_CM4_ADD0 - - 0x0 - 0x10 - W - - - - BOOT_CM4_ADD1 - - 0x10 - 0x10 - W - - - - - - - PCROP Protection - - - - - PROT_AREA_START1 - Flash Bank 1 PCROP start address - 0x0 - 0xC - R - - - - PROT_AREA_END1 - Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. - 0x10 - 0xC - R - - - - DMEP1 - - 0x1F - 0x1 - R - - Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START1 - Flash Bank 1 PCROP start address - 0x0 - 0xC - W - - - - PROT_AREA_END1 - Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - W - - - - DMEP1 - - 0x1F - 0x1 - W - - Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START2 - Flash Bank 2 PCROP start address - 0x0 - 0xC - R - - - - PROT_AREA_END2 - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - R - - - - DMEP2 - - 0x1F - 0x1 - R - - Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START2 - Flash Bank 2 PCROP start address - 0x0 - 0xC - W - - - - PROT_AREA_END2 - Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - W - - - - DMEP2 - - 0x1F - 0x1 - W - - Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - Secure Protection - - - - - SEC_AREA_START1 - Flash Bank 1 secure area start address - 0x0 - 0xC - R - - - - SEC_AREA_END1 - Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. - 0x10 - 0xC - R - - - - DMES1 - - 0x1F - 0x1 - R - - Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START1 - Flash Bank 1 secure area start address - 0x0 - 0xC - W - - - - SEC_AREA_END1 - Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. - 0x10 - 0xC - W - - - - DMES1 - - 0x1F - 0x1 - W - - Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START2 - Flash Bank 2 secure area start address - 0x0 - 0xC - R - - - - SEC_AREA_END2 - Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. - 0x10 - 0xC - R - - - - DMES2 - - 0x1F - 0x1 - R - - Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START2 - Flash Bank 2 secure area start address - 0x0 - 0xC - W - - - - SEC_AREA_END2 - Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. - 0x10 - 0xC - W - - - - DMES2 - - 0x1F - 0x1 - W - - Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - DTCM RAM Protection - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - R - - 2 KB - 4 KB - 8 KB - 16 KB - - - - - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - W - - 2 KB - 4 KB - 8 KB - 16 KB - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - R - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x0 - 0x1 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP0 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x0 - 0x1 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP8 - - 0x0 - 0x8 - R - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - nWRP8 - - 0x0 - 0x8 - W - - Write protection active on this sector - Write protection not active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x451.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x451.xml deleted file mode 100644 index 35fce476..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x451.xml +++ /dev/null @@ -1,725 +0,0 @@ - - - - 0x451 - STMicroelectronics - MCU - Cortex-M7 - STM32F76x/STM32F77x - STM32F7 - ARM 32-bit Cortex-M7 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x20 - - - - - - - - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - Single - 0x20 - - - - - - - - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - - - - - - - - - - - - - ITCM Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x20 - - - - - - - - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x1F - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x1E - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - nDBANK - - 0x1D - 0x1 - RW - - Flash in dual bank with 128 bits read access - Flash in single bank with 256 bits read access - - - - nDBOOT - - 0x1C - 0x1 - RW - - Dual Boot enabled - Dual Boot disabled - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x10 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x10 - 0xC - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x10 - 0x6 - RW - - Write protection active on bank1 sector 2i and 2i+1 - Write protection not active on bank1 sector 2i, 2i+1 - - - - nWRP6 - - 0x16 - 0x6 - RW - - Write protection active on bank2 sector 2i and 2i+1 - Write protection not active on bank2 sector 2i, 2i+1 - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0xF - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0xE - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - nDBANK - - 0xD - 0x1 - RW - - Flash in dual bank with 128 bits read access - Flash in single bank with 256 bits read access - - - - nDBOOT - - 0xC - 0x1 - RW - - Dual Boot enabled - Dual Boot disabled - - - - - - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - - - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x0 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0xC - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x0 - 0x6 - RW - - Write protection active on bank1 sector 2i and 2i+1 - Write protection not active on bank1 sector 2i, 2i+1 - - - - nWRP6 - - 0x6 - 0x6 - RW - - Write protection active on bank2 sector 2i and 2i+1 - Write protection not active on bank2 sector 2i, 2i+1 - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x452.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x452.xml deleted file mode 100644 index 8b0454c4..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x452.xml +++ /dev/null @@ -1,605 +0,0 @@ - - - - 0x452 - STMicroelectronics - MCU - Cortex-M7 - STM32F72x/STM32F73x - STM32F7 - ARM 32-bit Cortex-M7 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x10 - - - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - ITCM Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x10 - - - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x1F - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x1E - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x10 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x10 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - nWRP0 - - 0x10 - 0x4 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - Read/Write Protection - - - - - PCROP0 - - 0x0 - 0x8 - RW - - PCROP protection not active on this sector - PCROP protection active on this sector - - - - PCROP0 - - 0x0 - 0x4 - RW - - PCROP protection not active on this sector - PCROP protection active on this sector - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 (VBOR3), brownout threshold level 3 - BOR Level 2 (VBOR2), brownout threshold level 2 - BOR Level 1 (VBOR1), brownout threshold level 1 - BOR off, POR/PDR reset threshold level is applied - - - - - - - User Configuration - - - - - IWDG_STOP - - 0xF - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0xE - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x4 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x5 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - - - PCROP_RDP - - 0xF - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Boot address Option Bytes - - - - - BOOT_ADD0 - Define the boot address when BOOT0=0 - 0x0 - 0x10 - RW - - - - - - - - - BOOT_ADD1 - Define the boot address when BOOT0=1 - 0x0 - 0x10 - RW - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - RW - - Write protection active on this sector - Write protection not active on this sector - - - - - - - Read/Write Protection - - - - - PCROP0 - - 0x0 - 0x8 - RW - - PCROP protection not active on this sector - PCROP protection active on this sector - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x456.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x456.xml deleted file mode 100644 index 9a85e0f1..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x456.xml +++ /dev/null @@ -1,837 +0,0 @@ - - - - 0x456 - STMicroelectronics - MCU - Cortex-M0+ - STM32G051/STM32G061 - STM32G0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_HDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area B PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1B_END - Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x6 - RW - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1B_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x7 - RW - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x457.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x457.xml deleted file mode 100644 index 7de0f9e7..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x457.xml +++ /dev/null @@ -1,633 +0,0 @@ - - - - 0x457 - STMicroelectronics - MCU - Cortex-M0+ - STM32L01x/L02x - STM32L0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0x00 - RWE - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - R - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x10 - 0x4 - R - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x14 - 0x1 - R - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x15 - 0x1 - R - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x16 - 0x1 - R - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT_SEL - - 0x1D - 0x1 - R - - BOOT0 signal is defined by BOOT0 pin value (default mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT0 - When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode - 0x1E - 0x1 - R - - nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area - Main Flash memory is selected as boot area - - - - nBOOT1 - - 0x1F - 0x1 - R - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x4 - R - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x4 - R - - read/Write protection active - read/Write protection not active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - W - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - W - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - W - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - W - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - W - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT_SEL - - 0xD - 0x1 - W - - BOOT0 signal is defined by BOOT0 pin value (default mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT0 - When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode - 0xE - 0x1 - W - - Main Flash memory is selected as boot area - nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area - - - - nBOOT1 - - 0x0F - 0x1 - W - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x4 - W - - Write protection not active - Write protection active - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - WPRMOD - Sector protection mode selection option byte. - 0x8 - 0x1 - RW - - WRPx bit defines sector write protection - WRPx bit defines sector read/write (PCROP) protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x0 - 0x4 - RW - - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold the 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level OFF, reset level threshold for 1.45 V-1.55 V - BOR Level 1, reset level threshold for 1.69 V-1.8 V - BOR Level 2, reset level threshold for 1.94 V-2.1 V - BOR Level 3, reset level threshold for 2.3 V-2.49 V - BOR Level 4, reset level threshold for 2.54 V-2.74 V - BOR Level 5, reset level threshold for 2.77 V-3.0 V - - - - - - - User Configuration - - - - - IWDG_SW - - 0x4 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0x5 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x6 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nBOOT_SEL - - 0x0D - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (default mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT0 - When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode - 0x0E - 0x1 - RW - - Main Flash memory is selected as boot area - nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area - - - - nBOOT1 - - 0x0F - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - - - - Write Protection - - - - - WRPOT0 - - 0x0 - 0x4 - RW - - Write protection not active - Write protection active - - - - WRPOT0 - - 0x0 - 0x4 - RW - - read/Write protection active - read/Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x458.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x458.xml deleted file mode 100644 index 0e24985f..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x458.xml +++ /dev/null @@ -1,393 +0,0 @@ - - - - 0x458 - STMicroelectronics - MCU - Cortex-M4 - STM32F410 - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0x5 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0x5 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0x5 - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0x5 - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x460.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x460.xml deleted file mode 100644 index e16ef018..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x460.xml +++ /dev/null @@ -1,802 +0,0 @@ - - - - 0x460 - STMicroelectronics - MCU - Cortex-M0+ - STM32G07x/STM32G08x - STM32G0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 1, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area B PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x7 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 1, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x7 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x461.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x461.xml deleted file mode 100644 index d86041e9..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x461.xml +++ /dev/null @@ -1,839 +0,0 @@ - - - - 0x461 - STMicroelectronics - MCU - Cortex-M4 - STM32L496xx/STM32L4A6xx - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x462.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x462.xml deleted file mode 100644 index d3339a6f..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x462.xml +++ /dev/null @@ -1,653 +0,0 @@ - - - - 0x462 - STMicroelectronics - MCU - Cortex-M4 - STM32L45x/L46x - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x463.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x463.xml deleted file mode 100644 index 14965448..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x463.xml +++ /dev/null @@ -1,396 +0,0 @@ - - - - 0x463 - STMicroelectronics - MCU - Cortex-M4 - STM32F413/F423 - STM32F4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0x1F - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x10 - 0xF - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x10 - 0xF - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - PCROP Protection - - - - - SPRMOD - Selection of protection mode for nWPRi bits. - 0xF - 0x1 - RW - - PCROP disabled. nWPRi bits used for Write protection on sector i - PCROP enabled. nWPRi bits used for PCROP protection on sector i - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - RW - - BOR Level 3 reset threshold level from 2.70 to 3.60 V - BOR Level 2 reset threshold level from 2.40 to 2.70 V - BOR Level 1 reset threshold level from 2.10 to 2.40 V - BOR OFF reset threshold level from 1.80 to 2.10 V - - - - - - - User Configuration - - - - - WDG_SW - - 0x5 - 0x1 - RW - - Hardware watchdog - Software watchdog - - - - nRST_STOP - - 0x6 - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0x7 - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - - - - Write Protection - - - - - WRP0 - - 0x0 - 0xF - RW - - Write protection active - Write protection not active - - - - WRP0 - - 0x0 - 0xF - RW - - PCROP protection not active on sector i - PCROP protection active on sector i - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x464.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x464.xml deleted file mode 100644 index d7bdef5f..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x464.xml +++ /dev/null @@ -1,653 +0,0 @@ - - - - 0x464 - STMicroelectronics - MCU - Cortex-M4 - STM32L41x - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x466.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x466.xml deleted file mode 100644 index 4caeea63..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x466.xml +++ /dev/null @@ -1,828 +0,0 @@ - - - - 0x466 - STMicroelectronics - MCU - Cortex-M0+ - STM32G03x/STM32G04x - STM32G0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_HDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 1, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area B PCROP start address - 0x0 - 0x8 - RW - - - - - - - - - PCROP1B_END - Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x8 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x6 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 1, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory area size - 0x0 - 0x7 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x467.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x467.xml deleted file mode 100644 index 424562d9..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x467.xml +++ /dev/null @@ -1,1096 +0,0 @@ - - - - 0x467 - STMicroelectronics - MCU - - Cortex-M0+ - STM32G0B1xx/C1xx - STM32G0 - ARM 32-bit Cortex-M0+ based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area B PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - - - PCROP2A_STRT - Flash Area A PCROP2 start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP2A_END - Flash Area A PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - - - PCROP2B_STRT - Flash Area B PCROP2 start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP2B_END - Flash Area B PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - WRP2A_STRT - The address of the first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of the last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of the first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of the last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory for Bank 1 - 0x0 - 0x8 - RW - - - SEC_SIZE2 - Securable memory for Bank 2 On Dual Bank device,otherwise reserved - 0x14 - 0x8 - RW - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_EN - - 0x8 - 0x1 - RW - - Configurable brown out reset disabled, power-on reset defined by POR/PDR levels - Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account - - - - BORF_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x2 - RW - - BOR falling level 1 with threshold around 2.0 V - BOR falling level 2 with threshold around 2.2 V - BOR falling level 3 with threshold around 2.5 V - BOR falling level 4 with threshold around 2.8 V - - - - BORR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0xB - 0x2 - RW - - BOR rising level 1 with threshold around 2.1 V - BOR rising level 2 with threshold around 2.3 V - BOR rising level 3 with threshold around 2.6 V - BOR rising level 4 with threshold around 2.9 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xD - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xE - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xF - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - RAM_PARITY_CHECK - - 0x16 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nBOOT_SEL - - 0x18 - 0x1 - RW - - BOOT0 signal is defined by BOOT0 pin value (legacy mode) - BOOT0 signal is defined by nBOOT0 option bit - - - - nBOOT1 - - 0x19 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - nBOOT0 - - 0x1A - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - NRST_MODE - - 0x1B - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1D - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area A PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - - - PCROP2A_STRT - Flash Area A PCROP2 start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP2A_END - Flash Area A PCROP2 End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - - - PCROP2B_STRT - Flash Bank 2 PCROP2 start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP2B_END - Flash Bank 2 PCROP2 End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - WRP2A_STRT - The address of the first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of the last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of the first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of the last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - - FLASH security - - - - - BOOT_LOCK - used to force boot from user area - 0x10 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from Main Flash memory - - - - SEC_SIZE - Securable memory for Bank 1 - 0x0 - 0x8 - RW - - - SEC_SIZE2 - Securable memory for Bank 2 On Dual Bank device,otherwise reserved - 0x14 - 0x8 - RW - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x468.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x468.xml deleted file mode 100644 index 52930f42..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x468.xml +++ /dev/null @@ -1,759 +0,0 @@ - - - - 0x468 - STMicroelectronics - MCU - Cortex-M4 - STM32G43x/G44x - STM32G4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xE - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xE - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - Secure Protection - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xE - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xE - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x6 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x6 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x6 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x6 - RW - - - - - - - - - - Secure Protection - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x469.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x469.xml deleted file mode 100644 index 8319636f..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x469.xml +++ /dev/null @@ -1,1214 +0,0 @@ - - - - 0x469 - STMicroelectronics - MCU - Cortex-M4 - STM32G47x/G48x - STM32G4 - Category 3 devices, ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DBANK - - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xF - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xF - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0xF - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0xF - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - Secure Protection (Bank 1) - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - Secure Protection (Bank 2) - - - - - SEC_SIZE2 - sets the number of pages used in the bank 2 securable area - 0x0 - 0x8 - RW - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - - - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DBANK - - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xF - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0xF - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0xF - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0xF - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0xF - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - Secure Protection - - - - - SEC_SIZE2 - sets the number of pages used in the bank 2 securable area - 0x0 - 0x8 - RW - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x470.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x470.xml deleted file mode 100644 index dc74ca98..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x470.xml +++ /dev/null @@ -1,1350 +0,0 @@ - - - - 0x470 - STMicroelectronics - MCU - Cortex-M4 - STM32L4Rxxx/STM32L4Sxxx - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x8 - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DB1M - Dual-Bank on 1 MB Flash or 512 KB Flash memory devices - 0x15 - 0x1 - RW - - 1 MB or 512 Kb single Flash: contiguous address in bank1 - 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. - - - - DBANK - This bit can only be written when PCROPA/B is disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x11 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_STRT - The address of the last page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DB1M - Dual-Bank on 1 MB Flash or 512 KB Flash memory devices - 0x15 - 0x1 - RW - - 1 MB or 512 Kb single Flash: contiguous address in bank1 - 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. - - - - DBANK - This bit can only be written when PCROPA/B is disabled. - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x11 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x471.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x471.xml deleted file mode 100644 index ae94939f..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x471.xml +++ /dev/null @@ -1,1351 +0,0 @@ - - - - 0x471 - STMicroelectronics - MCU - Cortex-M4 - STM32L4Pxxx/STM32L4Qxxx - STM32L4 - ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x8 - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Dual - 0x4 - - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DB1M - Dual-Bank on 1 MB Flash or 512 KB Flash memory devices - 0x15 - 0x1 - RW - - 1 MB or 512 Kb single Flash: contiguous address in bank1 - 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. - - - - DBANK - This bit can only be written when PCROPA/B is disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. - 0x17 - 0x1 - RW - - Boot from embedded SRAM1 when BOOT0=1 - Boot from system memory when BOOT0=1 - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_STRT - The address of the last page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x11 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x11 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DB1M - Dual-Bank on 1 MB Flash or 512 KB Flash memory devices - 0x15 - 0x1 - RW - - 1 MB or 512 Kb single Flash: contiguous address in bank1 - 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. - - - - DBANK - This bit can only be written when PCROPA/B is disabled. - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - BOOT0 = 1, boot memory depends on nBOOT1 value - BOOT0 = 0, boot from main flash memory - - - - - - - PCROP Protection (Bank 1) - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP1_END - Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection (Bank 1) - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - PCROP Protection (Bank 2) - - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - PCROP2_STRT - Flash Bank 2 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP2_END - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - - - - Write Protection (Bank 2) - - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_STRT - The address of first page of the Bank 2 WRP first area - 0x0 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - WRP2A_END - The address of last page of the Bank 2 WRP first area - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_STRT - The address of first page of the Bank 2 WRP second area - 0x0 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - WRP2B_END - The address of last page of the Bank 2 WRP second area - 0x10 - 0x7 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x472.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x472.xml deleted file mode 100644 index 4b0501eb..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x472.xml +++ /dev/null @@ -1,3160 +0,0 @@ - - - - 0x472 - STMicroelectronics - MCU - Cortex-M33 - STM32L5xx - STM32L5 - ARM 32-bit Cortex-M33 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Single - - - - - - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x8 - - - - - - - - - - Single - 0x8 - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - Single - 0x8 - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Dual - 0x8 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0xFF - RWE - - - - Single - 0x8 - - - - - - - - - - Single - 0x8 - - - - - - - - - - Single - 0x8 - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - - - - - - Single - 0x8 - - - - - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - - - - - Option Bytes - Configuration - - RW - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DB256 - Dual-Bank on 256 Kb Flash memory devices - 0x15 - 0x1 - RW - - 256Kb single Flash: contiguous address in bank1 - 256Kb dual-bank Flash with contiguous addresses - - - - DBANK - This bit can only be written when all protection (secure, PCROP, HDP) are disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - - - HDP1EN - Hide protection first area enable - 0x1F - 0x1 - RW - - No HDP area 1 - HDP first area is enabled - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DB256 - Dual-Bank on 256 Kb Flash memory devices - 0x15 - 0x1 - RW - - 256Kb single Flash: contiguous address in bank1 - 256Kb dual-bank Flash with contiguous addresses - - - - DBANK - This bit can only be written when all protection (secure, PCROP, HDP) are disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DB256 - Dual-Bank on 256 Kb Flash memory devices - 0x15 - 0x1 - RW - - 256Kb single Flash: contiguous address in bank1 - 256Kb dual-bank Flash with contiguous addresses - - - - DBANK - This bit can only be written when all protection (secure, PCROP, HDP) are disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - - - HDP1EN - Hide protection first area enable - 0x1F - 0x1 - RW - - No HDP area 1 - HDP first area is enabled - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DB256 - Dual-Bank on 256 Kb Flash memory devices - 0x15 - 0x1 - RW - - 256Kb single Flash: contiguous address in bank1 - 256Kb dual-bank Flash with contiguous addresses - - - - DBANK - This bit can only be written when all protection (secure, PCROP, HDP) are disabled - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - - - HDP1EN - Hide protection first area enable - 0x1F - 0x1 - RW - - No HDP area 1 - HDP first area is enabled - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - Secure area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - Secure area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x479.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x479.xml deleted file mode 100644 index 6174b18c..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x479.xml +++ /dev/null @@ -1,892 +0,0 @@ - - - - 0x479 - STMicroelectronics - MCU - Cortex-M4 - STM32G491xC/E - STM32G4 - Category 3 devices, ARM 32-bit Cortex-M4 based device - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x10 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DBANK - - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - PB4_PUEN - - 0x16 - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_STRT - The address of the first page of WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of WRP first area - 0x10 - 0x8 - RW - - - - WRP1A_END - The address of the last page of WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_STRT - The address of the first page of WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of WRP second area - 0x10 - 0x8 - RW - - - - WRP1B_END - The address of the last page of WRP second area - 0x10 - 0x8 - RW - - - - - - - Secure Protection - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, no debug - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - BFB2 - - 0x14 - 0x1 - RW - - Dual-bank boot disable - Dual-bank boot enable - - - - DBANK - - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 - Boot from Flash if BOOT0 = 0, otherwise system memory - - - - SRAM_PE - SRAM1 and CCM SRAM parity check enable - 0x18 - 0x1 - RW - - SRAM1 and CCM SRAM parity check enable - SRAM1 and CCM SRAM parity check disable - - - - CCMSRAM_RST - CCM SRAM Erase when system reset - 0x19 - 0x1 - RW - - CCM SRAM erased when a system reset occurs - CCM SRAM is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PB8/BOOT0 pin - - - - nBOOT0 - This option bit sets the BOOT0 value only when nSWBOOT0=0 - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - NRST_MODE - - 0x1C - 0x2 - RW - - Reserved - Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin - GPIO: standard GPIO pad functionality, only internal RESET possible - Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) - - - - IRHEN - Internal reset holder enable bit - 0x1E - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin - Internal resets drives NRST pin low until it is seen as low level - - - - PB4_PUEN - - 0x16 - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - - - - PCROP Protection - - - - - PCROP1_STRT - Flash Bank 1 PCROP start address - 0x0 - 0x10 - RW - - - - - - - - - PCROP1_END - Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 - 0x0 - 0x10 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_STRT - The address of the first page of WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of WRP first area - 0x10 - 0x8 - RW - - - - WRP1A_END - The address of the last page of WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_STRT - The address of the first page of WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of WRP second area - 0x10 - 0x8 - RW - - - - WRP1B_END - The address of the last page of WRP second area - 0x10 - 0x8 - RW - - - - - - - Secure Protection - - - - - SEC_SIZE1 - sets the number of pages used in the bank 1 securable area - 0x0 - 0x8 - RW - - - BOOT_LOCK - Unique boot entry point - 0x10 - 0x1 - RW - - This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. - the boot will be done from user flash only, whatever the RDP level - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x480.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x480.xml deleted file mode 100644 index ec7f7ccd..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x480.xml +++ /dev/null @@ -1,846 +0,0 @@ - - - - 0x480 - STMicroelectronics - MCU - Cortex-M7 - STM32H7A/B - STM32H7 - ARM 32-bit Cortex-M7 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x20 - - - - - - - - - - - - - - - - Dual - 0x20 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x20 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - R - - reset level OFF - reset level is set to 2.1 V - reset level is set to 2.4 V - reset level is set to 2.7 V - - - - - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - W - - reset level OFF - reset level is set to 2.1 V - reset level is set to 2.4 V - reset level is set to 2.7 V - - - - - - - User Configuration - - - - - IWDG1_SW - - 0x4 - 0x1 - R - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP - - 0x6 - 0x1 - R - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY - - 0x7 - 0x1 - R - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - VDDMMC_HSLV - - 0x10 - 0x1 - R - - I/O speed optimization at low-voltage disabled - VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - IWDG_FZ_STOP - - 0x11 - 0x1 - R - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - IWDG_FZ_SDBY - - 0x12 - 0x1 - R - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - R - - Security feature disabled - Security feature enabled - - - - VDDIO_HSLV - - 0x1D - 0x1 - R - - Product working in the full voltage range,I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed - - - - SWAP_BANK_OPT - - 0x1F - 0x1 - R - - after boot loading, no swap for user sectors - after boot loading, user sectors swapped - - - - - - - - - IWDG1_SW - - 0x4 - 0x1 - W - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP - - 0x6 - 0x1 - W - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY - - 0x7 - 0x1 - W - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - VDDMMC_HSLV - - 0x10 - 0x1 - W - - I/O speed optimization at low-voltage disabled - VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - IWDG_FZ_STOP - - 0x11 - 0x1 - W - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - IWDG_FZ_SDBY - - 0x12 - 0x1 - W - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - W - - Security feature disabled - Security feature enabled - - - - VDDIO_HSLV - - 0x1D - 0x1 - W - - Product working in the full voltage range,I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed - - - - SWAP_BANK_OPT - - 0x1F - 0x1 - W - - after boot loading, no swap for user sectors - after boot loading, user sectors swapped - - - - - - - Boot address Option Bytes - - - - - BOOT_CM7_ADD0 - Define the boot address for Cortex-M7 when BOOT0=0 - 0x0 - 0x10 - R - - - - BOOT_CM7_ADD1 - Define the boot address for Cortex-M7 when BOOT0=1 - 0x10 - 0x10 - R - - - - - - - - - BOOT_CM7_ADD0 - - 0x0 - 0x10 - W - - - - BOOT_CM7_ADD1 - - 0x10 - 0x10 - W - - - - - - - PCROP Protection - - - - - PROT_AREA_START1 - Flash Bank 1 PCROP start address - 0x0 - 0xC - R - - - - PROT_AREA_END1 - Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. - 0x10 - 0xC - R - - - - DMEP1 - - 0x1F - 0x1 - R - - Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START1 - Flash Bank 1 PCROP start address - 0x0 - 0xC - W - - - - PROT_AREA_END1 - Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - W - - - - DMEP1 - - 0x1F - 0x1 - W - - Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START2 - Flash Bank 2 PCROP start address - 0x0 - 0xC - R - - - - PROT_AREA_END2 - Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - R - - - - DMEP2 - - 0x1F - 0x1 - R - - Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START2 - Flash Bank 2 PCROP start address - 0x0 - 0xC - W - - - - PROT_AREA_END2 - Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - W - - - - DMEP2 - - 0x1F - 0x1 - W - - Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - Secure Protection - - - - - SEC_AREA_START1 - Flash Bank 1 secure area start address - 0x0 - 0xC - R - - - - SEC_AREA_END1 - Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. - 0x10 - 0xC - R - - - - DMES1 - - 0x1F - 0x1 - R - - Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START1 - Flash Bank 1 secure area start address - 0x0 - 0xC - W - - - - SEC_AREA_END1 - Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. - 0x10 - 0xC - W - - - - DMES1 - - 0x1F - 0x1 - W - - Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START2 - Flash Bank 2 secure area start address - 0x0 - 0xC - R - - - - SEC_AREA_END2 - Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. - 0x10 - 0xC - R - - - - DMES2 - - 0x1F - 0x1 - R - - Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START2 - Flash Bank 2 secure area start address - 0x0 - 0xC - W - - - - SEC_AREA_END2 - Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. - 0x10 - 0xC - W - - - - DMES2 - - 0x1F - 0x1 - W - - Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - DTCM RAM Protection - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - R - - 2 KB - 4 KB - 8 KB - 16 KB - - - - - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - W - - 2 KB - 4 KB - 8 KB - 16 KB - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x20 - R - - Write protection active - Write protection not active - - - - - - - - - nWRP0 - - 0x0 - 0x20 - W - - Write protection active - Write protection not active - - - - - - - - - nWRP32 - - 0x0 - 0x20 - R - - Write protection active - Write protection not active - - - - - - - - - nWRP32 - - 0x0 - 0x20 - W - - Write protection active - Write protection not active - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x481.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x481.xml deleted file mode 100644 index a4214ec1..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x481.xml +++ /dev/null @@ -1,2484 +0,0 @@ - - - - 0x481 - STMicroelectronics - MCU - Cortex-M33 - STM32U5xx - STM32U5 - ARM 32-bit Cortex-M33 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x10 - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0xFF - RWE - - - - Single - 0x4 - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank Flash with contiguous address in bank 1 - Dual-bank Flash with contiguous addresses - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x8 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x8 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x8 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x8 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x8 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x8 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x8 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x8 - RW - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x8 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x8 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x8 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x8 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x8 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x8 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x8 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x8 - RW - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank Flash with contiguous address in bank 1 - Dual-bank Flash with contiguous addresses - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x8 - RW - - - - UNLOCK - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x482.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x482.xml deleted file mode 100644 index 43394dde..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x482.xml +++ /dev/null @@ -1,2502 +0,0 @@ - - - - 0x482 - STMicroelectronics - MCU - Cortex-M33 - STM32U5xx - STM32U5 - ARM 32-bit Cortex-M33 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - Single - 0x10 - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Single - 0x10 - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0xFF - RWE - - - - Single - 0x4 - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - - Single - 0x4 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank Flash with contiguous address in bank 1 - Dual-bank Flash with contiguous addresses - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1A - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1B - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2A - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2B - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1A - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1B - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2A - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2B - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the VDD supply level threshold that activates/releases the reset. - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - SRAM134_RST - SRAM1, SRAM3 and SRAM4 erase upon system reset - 0xF - 0x1 - RW - - SRAM1, SRAM3 and SRAM4 erased when a system reset occurs - SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x15 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - BKPRAM_ECC - SRAM2 parity check enable - 0x16 - 0x1 - RW - - Backup RAM ECC check enabled - Backup RAM ECC check disabled - - - - SRAM3_ECC - SRAM3 ECC detection and correction enable - 0x17 - 0x1 - RW - - SRAM3 ECC check enabled - SRAM3 ECC check disabled - - - - SRAM2_ECC - SRAM2 ECC detection and correction enable - 0x18 - 0x1 - RW - - SRAM2 ECC check enabled - SRAM2 ECC check disabled - - - - IO_VDD_HSLV - High-speed IO at low VDD voltage configuration bit - 0x1D - 0x1 - RW - - High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) - High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) - - - - IO_VDDIO2_HSLV - High-speed IO at low VDDIO2 voltage configuration bit - 0x1E - 0x1 - RW - - High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) - High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - Boot Configuration - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - - - SECBOOTADD0 - Secure boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - BOOT_LOCK - The boot is always forced to base address value programmed in SECBOOTADD0 - 0x0 - 0x1 - RW - - Boot based on the pad/option bit configuration - Boot forced from base address memory - - - - - - - Secure Area 1 - - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PSTRT - Start page of first secure area - 0x0 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - SECWM1_PEND - End page of first secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1A - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_1B - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - - - Secure Area 2 - - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PSTRT - Start page of second secure area - 0x0 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - SECWM2_PEND - End page of second secure area - 0x10 - 0x7 - RW - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2A - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK_2B - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) - Level 1, read protection of memories - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x8 - 0x3 - RW - - BOR Level 0, reset level threshold is around 1.7 V - BOR Level 1, reset level threshold is around 2.0 V - BOR Level 2, reset level threshold is around 2.2 V - BOR Level 3, reset level threshold is around 2.5 V - BOR Level 4, reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering Stop mode - No reset generated when entering Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering Standby mode - No reset generated when entering Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independant watchdog - Software independant watchdog - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Freeze IWDG counter in stop mode - IWDG counter active in stop mode - - - - IWDG_STDBY - - 0x12 - 0x1 - RW - - Freeze IWDG counter in standby mode - IWDG counter active in standby mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - SWAP_BANK - - 0x14 - 0x1 - RW - - Bank 1 and bank 2 address are not swapped - Bank 1 and bank 2 address are swapped - - - - DB256 - Dual-Bank on 256 Kb Flash memory devices - 0x15 - 0x1 - RW - - 256Kb single Flash: contiguous address in bank1 - 256Kb dual-bank Flash with contiguous addresses - - - - DBANK - Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices - 0x16 - 0x1 - RW - - Single bank mode with 128 bits data read width - Dual bank mode with 64 bits data - - - - SRAM2_PE - SRAM2 parity check enable - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - SRAM2_RST - SRAM2 Erase when system reset - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - nSWBOOT0 - Software BOOT0 - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - nBOOT0 - nBOOT0 option bit - 0x1B - 0x1 - RW - - nBOOT0 = 0 - nBOOT0 = 1 - - - - PA15_PUPEN - PA15 pull-up enable - 0x1C - 0x1 - RW - - USB power delivery dead-battery enabled/ TDI pull-up deactivated - USB power delivery dead-battery disabled/ TDI pull-up activated - - - - TZEN - Global TrustZone security enable - 0x1F - 0x1 - RW - - Global TrustZone security disabled - Global TrustZone security enabled - - - - - - - - - HDP1EN - Hide protection first area enable - 0x1F - 0x1 - RW - - No HDP area 1 - HDP first area is enabled - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - HDP1_PEND - End page of first hide protection area - 0x10 - 0x7 - RW - - - - - - - - - HDP2EN - Hide protection second area enable - 0x1F - 0x1 - RW - - No HDP area 2 - HDP second area is enabled - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - HDP2_PEND - End page of second hide protection area - 0x10 - 0x7 - RW - - - - - - - - - NSBOOTADD0 - Non-secure Boot base address 0 - 0x7 - 0x19 - RW - - - - - - - - - NSBOOTADD1 - Non-secure Boot base address 1 - 0x7 - 0x19 - RW - - - - - - - Write Protection 1 - - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PSTRT - Bank 1 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP1A_PEND - Bank 1 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK - Bank 1 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP1A start and end pages locked - WRP1A start and end pages unlocked - - - - - - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PSTRT - Bank 1 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP1B_PEND - Bank 1 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK - Bank 1 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP1B start and end pages locked - WRP1B start and end pages unlocked - - - - - - - - Write Protection 2 - - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PSTRT - Bank 2 WPR first area "A" start page - 0x0 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - WRP2A_PEND - Bank 2 WPR first area "A" end page - 0x10 - 0x7 - RW - - - - UNLOCK - Bank 2 WPR first area A unlock - 0x1F - 0x1 - RW - - WRP2A start and end pages locked - WRP2A start and end pages unlocked - - - - - - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PSTRT - Bank 2 WPR first area "B" start page - 0x0 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - WRP2B_PEND - Bank 2 WPR first area "B" end page - 0x10 - 0x7 - RW - - - - UNLOCK - Bank 2 WPR first area B unlock - 0x1F - 0x1 - RW - - WRP2B start and end pages locked - WRP2B start and end pages unlocked - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x483.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x483.xml deleted file mode 100644 index 94027fb3..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x483.xml +++ /dev/null @@ -1,655 +0,0 @@ - - - - 0x483 - STMicroelectronics - MCU - Cortex-M7 - STM32H72x/STM32H73x - STM32H7 - ARM 32-bit Cortex-M7 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x20 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - R - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x8 - 0x8 - W - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - R - - BOR OFF - BOR level1: 2.1V - BOR level2: 2.4 V - BOR level3: 2.7 V - - - - - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x2 - 0x2 - W - - reset level is set to 0.0 V - reset level is set to 2.1 V - reset level is set to 2.4 V - reset level is set to 2.7 V - - - - - - - User Configuration - - - - - IWDG1_SW - - 0x4 - 0x1 - R - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP - - 0x6 - 0x1 - R - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY - - 0x7 - 0x1 - R - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - IO_HSLV - - 0x1D - 0x1 - R - - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - FZ_IWDG_STOP - - 0x11 - 0x1 - R - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - FZ_IWDG_SDBY - - 0x12 - 0x1 - R - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - R - - Security feature disabled - Security feature enabled - - - - - - - - - IWDG1_SW - - 0x4 - 0x1 - W - - Independent watchdog is controlled by hardware - Independent watchdog is controlled by software - - - - NRST_STOP - - 0x6 - 0x1 - W - - STOP mode on Domain 1 is entering with reset - STOP mode on Domain 1 is entering without reset - - - - NRST_STBY - - 0x7 - 0x1 - W - - STANDBY mode on Domain 1 is entering with reset - STANDBY mode on Domain 1 is entering without reset - - - - IO_HSLV - - 0x1D - 0x1 - W - - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - FZ_IWDG_STOP - - 0x11 - 0x1 - W - - Independent watchdog is freezed in STOP mode - Independent watchdog is running in STOP mode - - - - FZ_IWDG_SDBY - - 0x12 - 0x1 - W - - Independent watchdog is freezed in STANDBY mode - Independent watchdog is running in STANDBY mode - - - - SECURITY - - 0x15 - 0x1 - W - - Security feature disabled - Security feature enabled - - - - SWAP_BANK_OPT - - 0x1F - 0x1 - W - - after boot loading, no swap for user sectors - after boot loading, user sectors swapped - - - - - - - Boot address Option Bytes - - - - - BOOT_CM7_ADD0 - Define the boot address for Cortex-M7 when BOOT0=0 - 0x0 - 0x10 - R - - - - BOOT_CM7_ADD1 - Define the boot address for Cortex-M7 when BOOT0=1 - 0x10 - 0x10 - R - - - - - - - - - BOOT_CM7_ADD0 - - 0x0 - 0x10 - W - - - - BOOT_CM7_ADD1 - - 0x10 - 0x10 - W - - - - - - - PCROP Protection - - - - - PROT_AREA_START - Flash Bank PCROP start address - 0x0 - 0xC - R - - - - PROT_AREA_END - Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address. - 0x10 - 0xC - R - - - - DMEP - - 0x1F - 0x1 - R - - Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - PROT_AREA_START - Flash Bank PCROP start address - 0x0 - 0xC - W - - - - PROT_AREA_END - Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP bit and changing RDP from level 1 to level 0 while putting end address greater than start address - 0x10 - 0xC - W - - - - DMEP - - 0x1F - 0x1 - W - - Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs - Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - Secure Protection - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - R - - 2 KB reserved to ST code - 4 KB reserved to ST code - 8 KB reserved to ST code - 16 KB reserved to ST code - - - - - - - - - ST_RAM_SIZE - - 0x13 - 0x2 - W - - 2 KB reserved to ST code - 4 KB reserved to ST code - 8 KB reserved to ST code - 16 KB reserved to ST code - - - - - - - - - SEC_AREA_START - Flash secure area start address - 0x0 - 0xC - R - - - - SEC_AREA_END - Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. - 0x10 - 0xC - R - - - - DMES - - 0x1F - 0x1 - R - - Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - - - SEC_AREA_START - Flash secure area start address - 0x0 - 0xC - W - - - - SEC_AREA_END - Flash secure area end address. If this address is equal to SEC_AREA_START, the whole flash memory is secure protected.If this address is lower than SEC_AREA_START, no protection is set on flash memory. - 0x10 - 0xC - W - - - - DMES - - 0x1F - 0x1 - W - - Flash secure area is kept when RDP level regression (change from level 1 to 0) occurs - Flash secure area is erased when RDP level regression (change from level 1 to 0) occurs - - - - - - - Write Protection - - - - - nWRP0 - - 0x0 - 0x8 - R - - Write protection active - Write protection not active - - - - - - - - - nWRP0 - - 0x0 - 0x8 - W - - Write protection active - Write protection not active - - - - - - - TCM_AXI Shared Configuration - - - - - TCM_AXI_SHARED - - 0x0 - 0x2 - R - - 64 KB ITCM : 320KB system AXI - 128KB ITCM : 256KB system AXI - 192KB ITCM : 192KB system AXI - 256KB ITCM : 128KB system AXI - - - - CPU_FREQ_BOOST - - 0x2 - 0x1 - R - - Feature disabled - CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) - - - - - - - - - TCM_AXI_SHARED - - 0x0 - 0x2 - W - - 64KB ITCM : 320KB system AXI - 128KB ITCM : 256KB system AXI - 192KB ITCM : 192KB system AXI - 256KB ITCM : 128KB system AXI - - - - CPU_FREQ_BOOST - - 0x2 - 0x1 - W - - Feature disabled - CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x484.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x484.xml deleted file mode 100644 index 2eed0fe8..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x484.xml +++ /dev/null @@ -1,2617 +0,0 @@ - - - - 0x484 - STMicroelectronics - MCU - Cortex-M33 - STM32H5xx - STM32H5 - ARM 32-bit Cortex-M33 based device - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Dual - 0x10 - - - - - - - - - - - - - - - Data EEPROM - Storage - The Data EEPROM memory block. It contains user data. - 0xFF - RWE - - - - - Dual - 0x4 - - - - - - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - - Product state - - - - - PRODUCT_STATE - Life state code. - 0x8 - 0x8 - R - - ST-VIRGIN - ST-OPEN - ST-SFI-READY - ST-ROT-READY - OEM-provisioning - OEM-provisioned - TZ-OEM-Closed - OEM-Closed - OEM-Locked - OEM-Unconstrained-Debug - OEM-NS-Unconstrained-Debug - - - - - - - - - PRODUCT_STATE - Life state code. - 0x8 - 0x8 - W - - ST-VIRGIN - ST-OPEN - ST-SFI-READY - ST-ROT-READY - OEM-provisioning - OEM-provisioned - TZ-OEM-Closed - OEM-Closed - OEM-Locked - OEM-Unconstrained-Debug - OEM-NS-Unconstrained-Debug - - - - - - - BOR Level - - - - - BOR_LEV - Brownout level option status bit. - 0x0 - 0x2 - R - - BOR OFF, POR/PDR reset threshold level is applied - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) - - - - - - - - - BOR_LEV - Brownout level option status bit. - 0x0 - 0x2 - W - - BOR OFF, POR/PDR reset threshold level is applied - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) - - - - - - - User Configuration - - - - - VDDIO_HSLV - VDD I/O high-speed at low-voltage status bit. - 0x10 - 0x4 - R - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - - - - - VDDIO_HSLV - VDD I/O high-speed at low-voltage status bit. - 0x10 - 0x4 - W - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - - - - - IWDG_STOP - Stop mode freeze option status bit. - 0x14 - 0x1 - R - Independent watchdog frozen in system Stop mode - Independent watchdog keep running in system Stop mode. - - - - - - - - IWDG_STOP - Stop mode freeze option status bit. - 0x14 - 0x1 - W - Independent watchdog frozen in system Stop mode - Independent watchdog keep running in system Stop mode. - - - - - - - - BOOT_UBE - Unique boot entry control, selects either ST or OEM iRoT for secure boot. - 0x16 - 0x8 - R - OEM-iRoT (system flash) selected - ST-iRoT (user flash) selected - - - - - - - - BOOT_UBE - Unique boot entry control, selects either ST or OEM iRoT for secure boot. - 0x16 - 0x8 - W - OEM-iRoT (system flash) selected - ST-iRoT (user flash) selected - - - - - - - - SWAP_BANK - Bank swapping option status bit. - 0x1F - 0x1 - R - bank 1 and bank 2 not swapped - bank 1 and bank 2 swapped - - - - - - - - SWAP_BANK - Bank swapping option status bit. - 0x1F - 0x1 - W - bank 1 and bank 2 not swapped - bank 1 and bank 2 swapped - - - - - - - - IWDG_SW - IWDG control mode option status bit. - 0x3 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - IWDG_SW - IWDG control mode option status bit. - 0x3 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - WWDG_SW - IWDG control mode option status bit. - 0x4 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - WWDG_SW - IWDG control mode option status bit. - 0x4 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_SHDWN - Core domain Shutdown entry reset option status bit. - 0x5 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_SHDWN - Core domain Shutdown entry reset option status bit. - 0x5 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_STOP - Core domain DStop entry reset option status bit. - 0x6 - 0x1 - R - a reset is generated when entering DStop or DStop2 mode on core domain - no reset generated when entering DStop or DStop2 mode on core domain - - - - - - - - NRST_STOP - Core domain DStop entry reset option status bit. - 0x6 - 0x1 - W - a reset is generated when entering DStop or DStop2 mode on core domain - no reset generated when entering DStop or DStop2 mode on core domain - - - - - - - - NRST_STDY - Core domain Standby entry reset option status bit. - 0x7 - 0x1 - R - a reset is generated when entering Standby mode on core domain - no reset generated when entering Standby mode on core domain - - - - - - - - NRST_STDY - Core domain Standby entry reset option status bit. - 0x7 - 0x1 - W - a reset is generated when entering Standby mode on core domain - no reset generated when entering Standby mode on core domain - - - - - - - - USB_EN - USB peripheral enable bit - 0xE - 0x1 - R - - USB communication disabled - USB communication enabled - - - - HASH_EN - HASH SHA IP enable bit. - 0xD - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - RNG_EN - random number generator IP enable bit - 0xC - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - PKA_EN - public key cryptography IP enable bit - 0xB - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - AES_EN - - 0xA - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - RSS_OPT - - 0x7 - 0x3 - R - - - - - - - FLASH_SIZE - - 0x4 - 0x3 - R - - 512kB product - 1MB product - 2MB product - - - - GFX_EN - GFX module option status bit - 0x3 - 0x1 - R - - GFX disabled - GFX enabled - - - - OTFDEC_EN - OTFDEC option status bit. Controls on the fly decryption of external memory - 0x2 - 0x1 - R - - OTFDEC disabled - OTFDEC enbled - - - - SAES_EN - Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage - 0x1 - 0x1 - R - - SAES disabled - SAES enabled - - - - CAN_EN - CAN module control bit - 0x0 - 0x1 - R - - CAN disabled - CAN enabled - - - - - - - - - USB_EN - USB peripheral enable bit. - 0xE - 0x1 - W - - USB communication disabled - USB communication enabled - - - - HASH_EN - HASH SHA IP enable bit. - 0xD - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - RNG_EN - random number generator IP enable bit - 0xC - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - PKA_EN - public key cryptography IP enable bit - 0xB - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - AES_EN - - 0xA - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - RSS_OPT - - 0x7 - 0x3 - W - - - - - - - FLASH_SIZE - - 0x4 - 0x3 - W - - 512kB product - 1MB product - 2MB product - - - - GFX_EN - GFX module option status bit - 0x3 - 0x1 - W - - GFX disabled - GFX enabled - - - - OTFDEC_EN - OTFDEC option status bit. Controls on the fly decryption of external memory - 0x2 - 0x1 - W - - OTFDEC disabled - OTFDEC enbled - - - - SAES_EN - Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage - 0x1 - 0x1 - W - - SAES disabled - SAES enabled - - - - CAN_EN - CAN module control bit - 0x0 - 0x1 - W - - CAN disabled - CAN enabled - - - - - - - - - - User Configuration 2 - - - - - TZEN - Trust Zone Enable configuration bits - 0x18 - 0x8 - R - - Trust zone disabled - Trust zone enabled - - - - HUK_PUF - This bit configures the nature and use of the unique key - 0xF - 0x1 - R - - The key is treated as HUK - The key is treated as PUF - - - - USBPD_DB_DIS - USB power delivery configuration option bit - 0x8 - 0x1 - R - - Disabled - Enabled - - - - SRAM2_PAR - Parity in SRAM2 region configuration bit - 0x7 - 0x1 - R - - The key is treated as HUK - The key is treated as PUF - - - - SRAM2_ECC - ECC in SRAM2 region configuration bit - 0x6 - 0x1 - R - - Disabled - Enabled - - - - SRAM3_ECC - ECC in SRAM3 region configuration bit - 0x5 - 0x1 - R - - Disabled - Enabled - - - - BKPRAM_ECC - ECC in BKPRAM region configuration bit - 0x4 - 0x1 - R - - Disabled - Enabled - - - - SRAM2_RST - - 0x3 - 0x1 - R - - Disabled - Enabled - - - - SRAM1_3_RST - - 0x2 - 0x1 - R - - Disabled - Enabled - - - - - - - - - TZEN - Trust Zone Enable configuration bits - 0x18 - 0x8 - W - - Trust zone disabled - Trust zone enabled - - - - HUK_PUF - This bit configures the nature and use of the unique key - 0xF - 0x1 - W - - The key is treated as HUK - The key is treated as PUF - - - - USBPD_DB_DIS - USB power delivery configuration option bit - 0x8 - 0x1 - W - - Disabled - Enabled - - - - SRAM2_PAR - Parity in SRAM2 region configuration bit - 0x7 - 0x1 - W - - The key is treated as HUK - The key is treated as PUF - - - - SRAM2_ECC - ECC in SRAM2 region configuration bit - 0x6 - 0x1 - W - - Disabled - Enabled - - - - SRAM3_ECC - ECC in SRAM3 region configuration bit - 0x5 - 0x1 - W - - Disabled - Enabled - - - - BKPRAM_ECC - ECC in BKPRAM region configuration bit - 0x4 - 0x1 - W - - Disabled - Enabled - - - - SRAM2_RST - - 0x3 - 0x1 - W - - Disabled - Enabled - - - - SRAM1_3_RST - - 0x2 - 0x1 - W - - Disabled - Enabled - - - - - - - - - - Boot Configuration - - - - - BOOT_ADDR_NS - Unique Boot Entry Secure Address - 0x8 - 0x10 - R - - - - BOOT_LOCK_NS - A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings - 0x0 - 0x8 - R - - - - - - - - - BOOT_ADDR_NS - Unique Boot Entry Secure Address - 0x8 - 0x10 - W - - - - BOOT_LOCK_NS - A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings - 0x0 - 0x8 - W - - - - - - - - - - Write sector group protection 1 - - - - - WRPSGn1 - Bank 1 sector group protection option status byte - 0x0 - 0x20 - R - - - - - - - - - WRPSGn1 - Bank 1 sector group protection option status byte - 0x0 - 0x20 - W - - - - - - - - - - Write sector group protection 2 - - - - - WRPSGn2 - Bank 2 sector group protection option status byte - 0x0 - 0x20 - R - - - - - - - - - WRPSGn2 - Bank 2 sector group protection option status byte - 0x0 - 0x20 - W - - - - - - - - - - OTP write protection - - - - - LOCKBL - OTP Block Lock - 0x0 - 0x20 - R - - - - - - - - - LOCKBL - OTP Block Lock - 0x0 - 0x20 - W - - - - - - - - - - Flash data sectors - - - - - DATA_EN - Bank1 Flash high-cycle data enable - 0xF - 0x1 - R - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_1 - DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. - 0x0 - 0x3 - R - - - - - - - - - DATA_EN - Bank1 Flash high-cycle data enable - 0xF - 0x1 - W - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_1 - DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. - 0x0 - 0x3 - W - - - - - - - - - - Flash data sectors - - - - - DATA_EN_2 - Bank1 Flash high-cycle data enable - 0xF - 0x1 - R - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_2 - DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. - 0x0 - 0x3 - R - - - - - - - - - DATA_EN_2 - Bank1 Flash high-cycle data enable - 0xF - 0x1 - W - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_2 - DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. - 0x0 - 0x3 - W - - - - - - - - - - Flash EPOCH - - - - - NS_EPOCH - Non Volatile Non Secure EPOCH counter - 0x0 - 0x18 - R - - - - - - - - - NS_EPOCH - Non Volatile Non Secure EPOCH counter - 0x0 - 0x18 - W - - - - - - - - - SEC_EPOCH - Non Volatile Secure EPOCH counter - 0x0 - 0x18 - R - - - - - - - - - SEC_EPOCH - Non Volatile Secure EPOCH counter - 0x0 - 0x18 - W - - - - - - - - - - Flash HDP bank 1 - - - - - HDP1_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - R - - - - HDP1_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - R - - - - - - - - - HDP1_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - W - - - - HDP1_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - W - - - - - - - - - - Flash HDP bank 2 - - - - - HDP2_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - R - - - - HDP2_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - R - - - - - - - - - HDP2_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - W - - - - HDP2_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - W - - - - - - - - - - - - Product state - - - - - PRODUCT_STATE - Life state code. - 0x8 - 0x8 - R - - ST-VIRGIN - ST-OPEN - ST-SFI-READY - ST-ROT-READY - OEM-provisioning - OEM-provisioned - TZ-OEM-Closed - OEM-Closed - OEM-Locked - OEM-Unconstrained-Debug - OEM-NS-Unconstrained-Debug - - - - - - - - - PRODUCT_STATE - Life state code. - 0x8 - 0x8 - W - - ST-VIRGIN - ST-OPEN - ST-SFI-READY - ST-ROT-READY - OEM-provisioning - OEM-provisioned - TZ-OEM-Closed - OEM-Closed - OEM-Locked - OEM-Unconstrained-Debug - OEM-NS-Unconstrained-Debug - - - - - - - BOR Level - - - - - BOR_LEV - Brownout level option status bit. - 0x0 - 0x2 - R - - BOR OFF, POR/PDR reset threshold level is applied - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) - - - - - - - - - BOR_LEV - Brownout level option status bit. - 0x0 - 0x2 - W - - BOR OFF, POR/PDR reset threshold level is applied - BOR Level 1, the threshold level is low (around 2.1 V) - BOR Level 2, the threshold level is medium (around 2.4 V) - BOR Level 3, the threshold level is high (around 2.7 V) - - - - - - - User Configuration - - - - - VDDIO_HSLV - VDD I/O high-speed at low-voltage status bit. - 0x10 - 0x4 - R - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - - - - - VDDIO_HSLV - VDD I/O high-speed at low-voltage status bit. - 0x10 - 0x4 - W - Product working in the full voltage range, I/O speed optimization at low-voltage disabled - VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed - - - - - - - - IWDG_STOP - Stop mode freeze option status bit. - 0x14 - 0x1 - R - Independent watchdog frozen in system Stop mode - Independent watchdog keep running in system Stop mode. - - - - - - - - IWDG_STOP - Stop mode freeze option status bit. - 0x14 - 0x1 - W - Independent watchdog frozen in system Stop mode - Independent watchdog keep running in system Stop mode. - - - - - - - - BOOT_UBE - Unique boot entry control, selects either ST or OEM iRoT for secure boot. - 0x16 - 0x8 - R - OEM-iRoT (system flash) selected - ST-iRoT (user flash) selected - - - - - - - - BOOT_UBE - Unique boot entry control, selects either ST or OEM iRoT for secure boot. - 0x16 - 0x8 - W - OEM-iRoT (system flash) selected - ST-iRoT (user flash) selected - - - - - - - - SWAP_BANK - Bank swapping option status bit. - 0x1F - 0x1 - R - bank 1 and bank 2 not swapped - bank 1 and bank 2 swapped - - - - - - - - SWAP_BANK - Bank swapping option status bit. - 0x1F - 0x1 - W - bank 1 and bank 2 not swapped - bank 1 and bank 2 swapped - - - - - - - - IWDG_SW - IWDG control mode option status bit. - 0x3 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - IWDG_SW - IWDG control mode option status bit. - 0x3 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - WWDG_SW - IWDG control mode option status bit. - 0x4 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - WWDG_SW - IWDG control mode option status bit. - 0x4 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_SHDWN - Core domain Shutdown entry reset option status bit. - 0x5 - 0x1 - R - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_SHDWN - Core domain Shutdown entry reset option status bit. - 0x5 - 0x1 - W - IWDG watchdog is controlled by hardware - IWDG watchdog is controlled by software - - - - - - - - NRST_STOP - Core domain DStop entry reset option status bit. - 0x6 - 0x1 - R - a reset is generated when entering DStop or DStop2 mode on core domain - no reset generated when entering DStop or DStop2 mode on core domain - - - - - - - - NRST_STOP - Core domain DStop entry reset option status bit. - 0x6 - 0x1 - W - a reset is generated when entering DStop or DStop2 mode on core domain - no reset generated when entering DStop or DStop2 mode on core domain - - - - - - - - NRST_STDY - Core domain Standby entry reset option status bit. - 0x7 - 0x1 - R - a reset is generated when entering Standby mode on core domain - no reset generated when entering Standby mode on core domain - - - - - - - - NRST_STDY - Core domain Standby entry reset option status bit. - 0x7 - 0x1 - W - a reset is generated when entering Standby mode on core domain - no reset generated when entering Standby mode on core domain - - - - - - - - USB_EN - USB peripheral enable bit - 0xE - 0x1 - R - - USB communication disabled - USB communication enabled - - - - HASH_EN - HASH SHA IP enable bit. - 0xD - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - RNG_EN - random number generator IP enable bit - 0xC - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - PKA_EN - public key cryptography IP enable bit - 0xB - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - AES_EN - - 0xA - 0x1 - R - - HASH feature disabled - HASH feature enabled - - - - RSS_OPT - - 0x7 - 0x3 - R - - - - - - - FLASH_SIZE - - 0x4 - 0x3 - R - - 512kB product - 1MB product - 2MB product - - - - GFX_EN - GFX module option status bit - 0x3 - 0x1 - R - - GFX disabled - GFX enabled - - - - OTFDEC_EN - OTFDEC option status bit. Controls on the fly decryption of external memory - 0x2 - 0x1 - R - - OTFDEC disabled - OTFDEC enbled - - - - SAES_EN - Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage - 0x1 - 0x1 - R - - SAES disabled - SAES enabled - - - - CAN_EN - CAN module control bit - 0x0 - 0x1 - R - - CAN disabled - CAN enabled - - - - - - - - - USB_EN - USB peripheral enable bit. - 0xE - 0x1 - W - - USB communication disabled - USB communication enabled - - - - HASH_EN - HASH SHA IP enable bit. - 0xD - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - RNG_EN - random number generator IP enable bit - 0xC - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - PKA_EN - public key cryptography IP enable bit - 0xB - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - AES_EN - - 0xA - 0x1 - W - - HASH feature disabled - HASH feature enabled - - - - RSS_OPT - - 0x7 - 0x3 - W - - - - - - - FLASH_SIZE - - 0x4 - 0x3 - W - - 512kB product - 1MB product - 2MB product - - - - GFX_EN - GFX module option status bit - 0x3 - 0x1 - W - - GFX disabled - GFX enabled - - - - OTFDEC_EN - OTFDEC option status bit. Controls on the fly decryption of external memory - 0x2 - 0x1 - W - - OTFDEC disabled - OTFDEC enbled - - - - SAES_EN - Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage - 0x1 - 0x1 - W - - SAES disabled - SAES enabled - - - - CAN_EN - CAN module control bit - 0x0 - 0x1 - W - - CAN disabled - CAN enabled - - - - - - - - - - User Configuration 2 - - - - - TZEN - Trust Zone Enable configuration bits - 0x18 - 0x8 - R - - Trust zone disabled - Trust zone enabled - - - - HUK_PUF - This bit configures the nature and use of the unique key - 0xF - 0x1 - R - - The key is treated as HUK - The key is treated as PUF - - - - USBPD_DB_DIS - USB power delivery configuration option bit - 0x8 - 0x1 - R - - Disabled - Enabled - - - - SRAM2_PAR - Parity in SRAM2 region configuration bit - 0x7 - 0x1 - R - - The key is treated as HUK - The key is treated as PUF - - - - SRAM2_ECC - ECC in SRAM2 region configuration bit - 0x6 - 0x1 - R - - Disabled - Enabled - - - - SRAM3_ECC - ECC in SRAM3 region configuration bit - 0x5 - 0x1 - R - - Disabled - Enabled - - - - BKPRAM_ECC - ECC in BKPRAM region configuration bit - 0x4 - 0x1 - R - - Disabled - Enabled - - - - SRAM2_RST - - 0x3 - 0x1 - R - - Disabled - Enabled - - - - SRAM1_3_RST - - 0x2 - 0x1 - R - - Disabled - Enabled - - - - - - - - - TZEN - Trust Zone Enable configuration bits - 0x18 - 0x8 - W - - Trust zone disabled - Trust zone enabled - - - - HUK_PUF - This bit configures the nature and use of the unique key - 0xF - 0x1 - W - - The key is treated as HUK - The key is treated as PUF - - - - USBPD_DB_DIS - USB power delivery configuration option bit - 0x8 - 0x1 - W - - Disabled - Enabled - - - - SRAM2_PAR - Parity in SRAM2 region configuration bit - 0x7 - 0x1 - W - - The key is treated as HUK - The key is treated as PUF - - - - SRAM2_ECC - ECC in SRAM2 region configuration bit - 0x6 - 0x1 - W - - Disabled - Enabled - - - - SRAM3_ECC - ECC in SRAM3 region configuration bit - 0x5 - 0x1 - W - - Disabled - Enabled - - - - BKPRAM_ECC - ECC in BKPRAM region configuration bit - 0x4 - 0x1 - W - - Disabled - Enabled - - - - SRAM2_RST - - 0x3 - 0x1 - W - - Disabled - Enabled - - - - SRAM1_3_RST - - 0x2 - 0x1 - W - - Disabled - Enabled - - - - - - - - - - Boot Configuration - - - - - BOOT_ADDR_NS - Unique Boot Entry Secure Address - 0x8 - 0x10 - R - - - - BOOT_LOCK_NS - A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings - 0x0 - 0x8 - R - - - - - - - - - BOOT_ADDR_NS - Unique Boot Entry Secure Address - 0x8 - 0x10 - W - - - - BOOT_LOCK_NS - A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings - 0x0 - 0x8 - W - - - - - - - - - - Write sector group protection 1 - - - - - WRPSGn1 - Bank 1 sector group protection option status byte - 0x0 - 0x20 - R - - - - - - - - - WRPSGn1 - Bank 1 sector group protection option status byte - 0x0 - 0x20 - W - - - - - - - - - - Write sector group protection 2 - - - - - WRPSGn2 - Bank 2 sector group protection option status byte - 0x0 - 0x20 - R - - - - - - - - - WRPSGn2 - Bank 2 sector group protection option status byte - 0x0 - 0x20 - W - - - - - - - - - - OTP write protection - - - - - LOCKBL - OTP Block Lock - 0x0 - 0x20 - R - - - - - - - - - LOCKBL - OTP Block Lock - 0x0 - 0x20 - W - - - - - - - - - - Flash data sectors - - - - - DATA_EN - Bank1 Flash high-cycle data enable - 0xF - 0x1 - R - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_1 - DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. - 0x0 - 0x3 - R - - - - - - - - - DATA_EN - Bank1 Flash high-cycle data enable - 0xF - 0x1 - W - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_1 - DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. - 0x0 - 0x3 - W - - - - - - - - - - Flash data sectors - - - - - DATA_EN_2 - Bank1 Flash high-cycle data enable - 0xF - 0x1 - R - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_2 - DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. - 0x0 - 0x3 - R - - - - - - - - - DATA_EN_2 - Bank1 Flash high-cycle data enable - 0xF - 0x1 - W - - No Flash high-cycle data area - Flash high-cycle data is used - - - - DATA_SECTOR_START_2 - DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. - 0x0 - 0x3 - W - - - - - - - - - - Flash EPOCH - - - - - NS_EPOCH - Non Volatile Non Secure EPOCH counter - 0x0 - 0x18 - R - - - - - - - - - NS_EPOCH - Non Volatile Non Secure EPOCH counter - 0x0 - 0x18 - W - - - - - - - - - SEC_EPOCH - Non Volatile Secure EPOCH counter - 0x0 - 0x18 - R - - - - - - - - - SEC_EPOCH - Non Volatile Secure EPOCH counter - 0x0 - 0x18 - W - - - - - - - - - - Flash HDP bank 1 - - - - - HDP1_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - R - - - - HDP1_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - R - - - - - - - - - HDP1_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - W - - - - HDP1_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - W - - - - - - - - - - Flash HDP bank 2 - - - - - HDP2_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - R - - - - HDP2_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - R - - - - - - - - - HDP2_STRT - TIL barrier start set in number of 8kb sectors - 0x0 - 0x7 - W - - - - HDP2_END - TIL barrier end set in number of 8kb sectors - 0x10 - 0x7 - W - - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x494.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x494.xml deleted file mode 100644 index 94dd62e6..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x494.xml +++ /dev/null @@ -1,1036 +0,0 @@ - - - - 0x494 - STMicroelectronics - MCU - Cortex-M0+/M4 - STM32WB1xxx - STM32WB - ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from code area if BOOT0=0 otherwise embedded SRAM1 - Boot from code area if BOOT0=0 otherwise system Flash - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - GPIO_MODE_PB11 - PB11 GPIO mode - 0x1C - 0x1 - RW - - If RESET_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode, GPIO functionality is not available on PB11. If RESET_MODE_PB11 = 1: Reset Input only, a low level on the NRST pin generates system reset, internal RESET. - If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11. - - - - RESET_MODE_PB11 - PB11 reset mode - 0x16 - 0x1 - RW - - If GPIO_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode. If GPIO_MODE_PB11 = 1: Standard GPIO pad functionality, only internal RESET possible. - If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode). - - - - IRH - Internal reset holder enable bit - 0xF - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin. - Internal resets drives NRST pin low until it is seen as low level. - - - - - - - ESE - - - - - ESE - System Security Enabled flag - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the WRP first area. - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the WRP first area. - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of WRP second area. - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of WRP second area. - 0x10 - 0x8 - RW - - - - - - - - - - IPCCDBA-AA - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - - - - - Security Configuration Option bytes - - - - - SFSA - Secure Flash Start Address - 0x0 - 0x8 - RW - - - - FSD - Flash Security Disable - 0x8 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - Disable CPU2 Debug access - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - CPU2 boot reset vector memory selection - 0x1F - 0x1 - RW - - SBRV will address SRAM1 or SRAM2 - SBRV will address Flash - - - - BRSD_B - Backup SRAM2b security disable - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SBRSA_B - SBRSA_B[1:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x2 - RW - - - - BRSD_A - Backup SRAM2a security disable - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA_A - SBRSA_A[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x11 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from code area if BOOT0=0 otherwise embedded SRAM1 - Boot from code area if BOOT0=0 otherwise system Flash - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - GPIO_MODE_PB11 - PB11 GPIO mode - 0x1C - 0x1 - RW - - If RESET_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode, GPIO functionality is not available on PB11. If RESET_MODE_PB11 = 1: Reset Input only, a low level on the NRST pin generates system reset, internal RESET. - If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11. - - - - RESET_MODE_PB11 - PB11 reset mode - 0x16 - 0x1 - RW - - If GPIO_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode. If GPIO_MODE_PB11 = 1: Standard GPIO pad functionality, only internal RESET possible. - If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode). - - - - IRH - Internal reset holder enable bit - 0xF - 0x1 - RW - - Internal resets are propagated as simple pulse on NRST pin. - Internal resets drives NRST pin low until it is seen as low level. - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration - - - - - ESE - System Security Enabled flag - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - - - SFSA - Secure Flash Start Address - 0x0 - 0x8 - RW - - - - FSD - Flash Security Disable - 0x8 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - Disable CPU2 Debug access - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - CPU2 boot reset vector memory selection - 0x1F - 0x1 - RW - - SBRV will address SRAM1 or SRAM2 - SBRV will address Flash - - - - BRSD_B - Backup SRAM2b security disable - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SBRSA_B - SBRSA_B[1:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x2 - RW - - - - BRSD_A - Backup SRAM2a security disable - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA_A - SBRSA_A[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x11 - RW - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the WRP second area. - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the WRP second area. - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x495.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x495.xml deleted file mode 100644 index f62a474d..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x495.xml +++ /dev/null @@ -1,961 +0,0 @@ - - - - 0x495 - STMicroelectronics - MCU - Cortex-M0+/M4 - STM32WB5x - STM32WB - ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 Boot selected based on nBOOT1 - nBOOT0=1 Boot from main Flash - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from code area if BOOT0=0 otherwise embedded SRAM - Boot from code area if BOOT0=0 otherwise system Flash - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration Option bytes - 1 - - - - - ESE - - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - Security Configuration Option bytes - 2 - - - - - SFSA - Secure Flash start address - 0x0 - 0x8 - RW - - - - FSD - - 0x8 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - - 0x1F - 0x1 - RW - - SBRV will address SRAM2 - SBRV will address Flash - - - - NBRSD - If FSD=1 : SRAM2b is non-secure. If FSD=0 : - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SNBRSA - SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x5 - RW - - - - BRSD - If FSD=1 : SRAM2a is non-secure. If FSD=0 : - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA - SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x12 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 Boot selected based on nBOOT1 - nBOOT0=1 Boot from main Flash - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from Flash if nBoot0=0 otherwise embedded SRAM - Boot from Flash if nBoot0=0 otherwise system memory - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration Option bytes - - - - - ESE - - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - - - SFSA - Secure Flash start address - 0x0 - 0x8 - RW - - - - FSD - - 0x8 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - - 0x1F - 0x1 - RW - - SBRV will address SRAM2 - SBRV will address Flash - - - - NBRSD - If FSD=1 : SRAM2b is non-secure. If FSD=0 : - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SNBRSA - SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x5 - RW - - - - BRSD - If FSD=1: SRAM2a is non-secure. If FSD=0 : - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA - SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x12 - RW - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x496.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x496.xml deleted file mode 100644 index e404ebae..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x496.xml +++ /dev/null @@ -1,948 +0,0 @@ - - - - 0x496 - STMicroelectronics - MCU - Cortex-M0+/M4 - STM32WB35xx - STM32WB - ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0x00 - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from code area if BOOT0=0 otherwise system Flash - Boot from code area if BOOT0=0 otherwise embedded SRAM - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration Option bytes - - - - - ESE - - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - - - SFSA - Secure Flash start address - 0x0 - 0x7 - RW - - - FSD - - 0x7 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - - 0x1F - 0x1 - RW - - SBRV will address SRAM2 - SBRV will address Flash - - - - NBRSD - If FSD=1 : SRAM2b is non-secure. If FSD=0 : - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SNBRSA - SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x5 - RW - - - BRSD - If FSD=1 : SRAM2a is non-secure. If FSD=0 : - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA - SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x11 - RW - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area. - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area. - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area. - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area. - 0x10 - 0x8 - RW - - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - - 0x17 - 0x1 - RW - - Boot from code area if BOOT0=0 otherwise system Flash - Boot from code area if BOOT0=0 otherwise embedded SRAM - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM2RST - - 0x19 - 0x1 - RW - - SRAM2 erased when a system reset occurs - SRAM2 is not erased when a system reset occurs - - - - SRAM2PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRSTSHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDGSW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGDSTDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDGSTOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDGSW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration Option bytes - - - - - ESE - - 0x8 - 0x1 - R - - Security disabled - Security enabled - - - - - - - - - SFSA - Secure Flash start address - 0x0 - 0x7 - RW - - - FSD - - 0x7 - 0x1 - RW - - System and Flash secure - System and Flash non-secure - - - - DDS - - 0xC - 0x1 - RW - - CPU2 debug access enabled - CPU2 debug access disabled - - - - - - - - - C2OPT - - 0x1F - 0x1 - RW - - SBRV will address SRAM2 - SBRV will address Flash - - - - NBRSD - If FSD=1 : SRAM2b is non-secure. If FSD=0 : - 0x1E - 0x1 - RW - - SRAM2b is secure - SRAM2b is non-secure - - - - SNBRSA - SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. - 0x19 - 0x5 - RW - - - BRSD - If FSD=1: SRAM2a is non-secure. If FSD=0 : - 0x17 - 0x1 - RW - - SRAM2a is secure - SRAM2a is non-secure - - - - SBRSA - SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. - 0x12 - 0x5 - RW - - - SBRV - Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. - 0x0 - 0x12 - RW - - - - - - PCROP Protection - - - - - PCROP1A_STRT - Flash Area 1 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1A_END - Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - Flash Area 2 PCROP start address - 0x0 - 0x9 - RW - - - - - - - - - PCROP1B_END - Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0. - 0x0 - 0x9 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - The address of the first page of the Bank 1 WRP first area - 0x0 - 0x8 - RW - - - - WRP1A_END - The address of the last page of the Bank 1 WRP first area - 0x10 - 0x8 - RW - - - - - - - - - WRP1B_STRT - The address of the first page of the Bank 1 WRP second area. - 0x0 - 0x8 - RW - - - - WRP1B_END - The address of the last page of the Bank 1 WRP second area. - 0x10 - 0x8 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x497.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x497.xml deleted file mode 100644 index 8f3be5de..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x497.xml +++ /dev/null @@ -1,1054 +0,0 @@ - - - - 0x497 - STMicroelectronics - MCU - Cortex-M0+/M4 - STM32WLxx - STM32WL - ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device - - - - - - - - - - - Embedded SRAM - Storage - - 0x00 - RWE - - - - - Single - - - - - - - - - - Embedded Flash - Storage - The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms - 0xFF - RWE - - - - - - Single - 0x8 - - - - - - - - - - OTP - Storage - The Data OTP memory block. It contains the one time programmable bits. - 0xFF - RW - - - - - Single - 0x8 - - - - - - - - - - MirrorOptionBytes - Storage - Mirror Option Bytes contains the extra area. - 0xFF - RW - - - - - Single - 0x4 - - - - - - - - - - Option Bytes - Configuration - - RW - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - Together with the BOOT0 pin or option bit nBOOT0, this bit selects boot mode from the user Flash memory, SRAM1 or system Flash memory . Refer to Reference Manual: Boot configuration Section. - 0x17 - 0x1 - RW - - - - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM_RST - - 0x19 - 0x1 - RW - - SRAM1 and SRAM2 are erased when a system reset occurs - SRAM1 and SRAM2 are not erased when a system reset occurs - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGD_STDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - BOOT_LOCK - - 0x1E - 0x1 - RW - - CPU1 CM4 Boot lock disabled - CPU1 CM4 Boot lock enabled - - - - C2BOOT_LOCK - - 0x1F - 0x1 - RW - - CPU2 CM0+ Boot lock disabled - CPU2 CM0+ Boot lock enabled - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - Security Configuration Option bytes ESE - - - - - ESE - - 0x8 - 0x1 - RW - - Security disabled - Security enabled - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - PCROP1A_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone A - 0x0 - 0x8 - RW - - - - - - - - - PCROP1A_END - PCROP1A_END[7:0] contain the last included 1kB page readout protected of the Flash area zone A - 0x0 - 0x8 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - PCROP1B_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone B - 0x0 - 0x8 - RW - - - - - - - - - PCROP1B_END - PCROP1B_END[7:0] contain the last included 1kB page readout protected of the Flash area zone B - 0x0 - 0x8 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - WRP1A_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone A. - 0x0 - 0x7 - RW - - - - WRP1A_END - WRP1A_END[6:0] contain the last included 2kB page write protected of the Flash area zone A. - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - WRP1B_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone B. - 0x0 - 0x7 - RW - - - - WRP1B_END - WRP1B_END[6:0] contain the last included 2kB page write protected of the Flash area zone B. - 0x10 - 0x7 - RW - - - - - - - - - - Security Configuration Option bytes - - - - - SFSA - This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area. - 0x0 - 0x7 - RW - - - FSD - - 0x7 - 0x1 - RW - - System and Flash secure. This bit can only be accessed when HDPADIS = 0 - System and Flash non-secure. This bit can only be accessed when HDPADIS = 0 - - - - DDS - - 0xC - 0x1 - RW - - CPU2 debug access enabled (when also enabled by C2SWDBGEN) - CPU2 debug access disabled (when also enabled by C2SWDBGEN) - - - - HDPSA - HDPSA[6:0] contain the start address of the first 2 kB page of the User Flash hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash hide protection area enabled. - 0x10 - 0x7 - RW - - - HDPAD - User Flash hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0 - 0x17 - 0x1 - RW - - User Flash hide protection area access enabled. - User Flash hide protection area access disabled. - - - - - SUBGHSPISD - SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled - 0x1F - 0x1 - RW - - FSD=0 and SUBGHSPISD=0: SPI3 security enabled - FSD=0 and SUBGHSPISD=1: SPI3 security disabled - - - - - - - - - C2OPT - - 0x1F - 0x1 - RW - - SBRV will address SRAM1 or SRAM2, from start address 0x2000 0000 + SBRV. - SBRV will address Flash memory, from start address 0x0800 0000 + SBRV. - - - - NBRSD - - 0x1E - 0x1 - RW - - SRAM1 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0 - SRAM1 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - - - - SNBRSA - SNBRSA[4:0] contain the start address of the first 1 kB page of the secure "non-backup" SRAM1 area. To keep the tool working you have to set a value greater or equal to 0xC - 0x19 - 0x5 - RW - - - BRSD - - 0x17 - 0x1 - RW - - SRAM2 is secure if FSD=0 and non-secure otherwise. This bit can only be accessed when HDPADIS = 0 - SRAM2 is non-secure if FSD=0 and secure otherwise. This bit can only be accessed when HDPADIS = 0 - - - - SBRSA - SBRSA[4:0] contain the start address of the first 1 kB page of the secure backup SRAM2 area. To keep the tool working you have to set a value less than 0x15 - 0x12 - 0x5 - RW - - - SBRV - SBRV[15:0] contain the word (4B) aligned CPU2 boot reset start address offset within the selected memory area by C2OPT. - 0x0 - 0x10 - RW - - - - - - - - - Read Out Protection - - - - - RDP - Read protection option byte. The read protection is used to protect the software code stored in Flash memory. - 0x0 - 0x8 - RW - - Level 0, no protection - or any value other than 0xAA and 0xCC: Level 1, read protection - Level 2, chip protection - - - - - - - BOR Level - - - - - BOR_LEV - These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory - 0x9 - 0x3 - RW - - BOR Level 0 reset level threshold is around 1.7 V - BOR Level 1 reset level threshold is around 2.0 V - BOR Level 2 reset level threshold is around 2.2 V - BOR Level 3 reset level threshold is around 2.5 V - BOR Level 4 reset level threshold is around 2.8 V - - - - - - - User Configuration - - - - - nBOOT0 - - 0x1B - 0x1 - RW - - nBOOT0=0 - nBOOT0=1 - - - - nBOOT1 - Together with the BOOT0 pin or option bit nBOOT0, this bit selects boot mode from the user Flash memory, SRAM1 or system Flash memory . Refer to Reference Manual: Boot configuration Section. - 0x17 - 0x1 - RW - - - - - - - nSWBOOT0 - - 0x1A - 0x1 - RW - - BOOT0 taken from the option bit nBOOT0 - BOOT0 taken from PH3/BOOT0 pin - - - - SRAM_RST - - 0x19 - 0x1 - RW - - SRAM1 and SRAM2 are erased when a system reset occurs - SRAM1 and SRAM2 are not erased when a system reset occurs - - - - SRAM2_PE - - 0x18 - 0x1 - RW - - SRAM2 parity check enable - SRAM2 parity check disable - - - - nRST_STOP - - 0xC - 0x1 - RW - - Reset generated when entering the Stop mode - No reset generated when entering the Stop mode - - - - nRST_STDBY - - 0xD - 0x1 - RW - - Reset generated when entering the Standby mode - No reset generated when entering the Standby mode - - - - nRST_SHDW - - 0xE - 0x1 - RW - - Reset generated when entering the Shutdown mode - No reset generated when entering the Shutdown mode - - - - WWDG_SW - - 0x13 - 0x1 - RW - - Hardware window watchdog - Software window watchdog - - - - IWGD_STDBY - - 0x12 - 0x1 - RW - - Independent watchdog counter frozen in Standby mode - Independent watchdog counter running in Standby mode - - - - IWDG_STOP - - 0x11 - 0x1 - RW - - Independent watchdog counter frozen in Stop mode - Independent watchdog counter running in Stop mode - - - - IWDG_SW - - 0x10 - 0x1 - RW - - Hardware independent watchdog - Software independent watchdog - - - - BOOT_LOCK - - 0x1E - 0x1 - RW - - CPU1 CM4 Boot lock disabled - CPU1 CM4 Boot lock enabled - - - - C2BOOT_LOCK - - 0x1F - 0x1 - RW - - CPU2 CM0+ Boot lock disabled - CPU2 CM0+ Boot lock enabled - - - - - - - - - IPCCDBA - IPCC mailbox data buffer base address - 0x0 - 0xE - RW - - - - - - - PCROP Protection - - - - - PCROP1A_STRT - PCROP1A_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone A - 0x0 - 0x8 - RW - - - - - - - - - PCROP1A_END - PCROP1A_END[7:0] contain the last included 1kB page readout protected of the Flash area zone A - 0x0 - 0x8 - RW - - - - PCROP_RDP - - 0x1F - 0x1 - RW - - PCROP zone is kept when RDP is decreased - PCROP zone is erased when RDP is decreased - - - - - - - - - PCROP1B_STRT - PCROP1B_STRT[7:0] contain the first included 1kB page readout protected of the Flash area zone B - 0x0 - 0x8 - RW - - - - - - - - - PCROP1B_END - PCROP1B_END[7:0] contain the last included 1kB page readout protected of the Flash area zone B - 0x0 - 0x8 - RW - - - - - - - Write Protection - - - - - WRP1A_STRT - WRP1A_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone A - 0x0 - 0x7 - RW - - - - WRP1A_END - WRP1A_END[6:0] contain the last included 2kB page write protected of the Flash area zone A - 0x10 - 0x7 - RW - - - - - - - - - WRP1B_STRT - WRP1B_STRT[6:0] contain the first included 2kB page write protected of the Flash area zone B - 0x0 - 0x7 - RW - - - - WRP1B_END - WRP1B_END[6:0] contain the last included 2kB page write protected of the Flash area zone B - 0x10 - 0x7 - RW - - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x500.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x500.xml deleted file mode 100644 index 6b190d73..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x500.xml +++ /dev/null @@ -1,1822 +0,0 @@ - - - - 0x500 - STMicroelectronics - MPU - Cortex-A7 - STM32MP1 - STM32MP - ARM 32-bit Cortex-A7 and ARM 32-bit Cortex-M4 dualprocessor based device, CPU clock up to 600MHz - - - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - OTP Memory - Configuration - - RW - - - - OTP - - - - - none - none - 0x0 - 0x20 - R - - - - - - - - TR - set SAFMEM Ring current level, default value = 0b00 - 0x7 - 0x2 - RW - - - PRGWIDTH - SAFMEM Programming Pulse Width, default value = 0b0001 - 0x3 - 0x4 - RW - - - FRC - SAFMEM CLOCK frequency range selection, default value = 0b11 - 0x1 - 0x2 - RW - - - PWRUP - SAFMEM Power up control - 0x0 - 0x1 - RW - - - - - - - - BIST2LOCK - 0: BIST2 is not locked, 1: BIST2 is locked. - 0x7 - 0x1 - R - - - BIST1LOCK - 0: BIST1 is not locked, 1: BIST1 is locked. - 0x6 - 0x1 - R - - - PWRON - 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. - 0x5 - 0x1 - R - - - PROGFAIL - 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. - 0x4 - 0x1 - R - - - BUSY - 0: SAFMEM is Idle, 1: SAFMEM operation is on going. - 0x3 - 0x1 - R - - - INVALID - 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. - 0x2 - 0x1 - R - - - FULLDBG - 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. - 0x1 - 0x1 - R - - - SECURE - 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. - 0x0 - 0x1 - R - - - - - - - - GPLOCK - 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. - 0x4 - 0x1 - RW - - - FENREG - 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. - 0x3 - 0x1 - RW - - - DENREG - 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. - 0x2 - 0x1 - RW - - - OTP - 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. - 0x0 - 0x1 - RW - - - - - - - - DBGSWENABLE - Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. - 0xA - 0x1 - RW - - - CFGSDISABLE - Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. - 0x9 - 0x1 - RW - - - CP15SDISABLE - Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. - 0x7 - 0x2 - RW - - - SPNIDEN - Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. - 0x6 - 0x1 - RW - - - SPIDEN - Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. - 0x5 - 0x1 - RW - - - HDPEN - Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. - 0x4 - 0x1 - RW - - - DEVICEEN - Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. - 0x3 - 0x1 - RW - - - NIDEN - Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. - 0x2 - 0x1 - RW - - - DBGEN - Debug enable with signal dbgen. 0: Disabled, 1: Enabled. - 0x1 - 0x1 - RW - - - DFTEN - DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. - 0x0 - 0x1 - RW - - - - - - - - CAN_disable - 0: CAN interface is enabled, 1: CAN interface is disabled. - 0x3 - 0x1 - RW - - - GPU_disable - 0: GPU enabled, 1: GPU disabled. - 0x2 - 0x1 - RW - - - Dual_A7_disable - 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. - 0x1 - 0x1 - RW - - - Crypto_disable - 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. - 0x0 - 0x1 - RW - - - - - - - - W_R conf - This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM - 0x0 - 0x1 - RW - - - - - - - - BSEC_OTP_DISTURBED0 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED1 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED2 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR0 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR1 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR2 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_WRLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK0 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK1 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK2 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK0 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK1 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK2 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - CFG0 - These bits determins the OTP mode encoding - 0x0 - 0x7 - RW - - - - - - - - fdis3 - Disable CAN - 0x3 - 0x1 - RW - - - fdis2 - Disable GPU - 0x2 - 0x1 - RW - - - fdis1 - Disable CPU1 - 0x1 - 0x1 - RW - - - fdis0 - Disable Crypto (license export) - 0x0 - 0x1 - RW - - - - - - - - rma_force - RMA force Bit - 0x0 - 0x1 - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - - - - - - CFG3 - These bits determins the BOOT source definition - 0x0 - 0x20 - RW - - - - - - - - CFG4 - These bits determins the BOOT monotonic counter - 0x0 - 0x20 - RW - - - - - - - - CFG5 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG6 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG7 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG8 - BOOT/Device configuration. - 0x2 - 0x1E - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - rma_lock - RMA lock Bit - 0x0 - 0x1 - RW - - - - - - - - CFG9 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG10 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG11 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG12 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - ID0 - Lot ID on 42bit (11LSB's) - 0x15 - 0xB - RW - - - ID0 - Wafer ID - 0x10 - 0x5 - RW - - - ID0 - Wafer Y coordinates - 0x8 - 0x8 - RW - - - ID0 - Wafer X coordinates - 0x0 - 0x8 - RW - - - - - - - - ID1 - Lot ID on 42bit (31MSB's) - 0x0 - 0x20 - RW - - - - - - - - ID2 - Test program flow T[12],F[12],Q[12] - 0x14 - 0xC - RW - - - ID2 - FT program revision - 0xA - 0xA - RW - - - ID2 - EWS program revision - 0x0 - 0xA - RW - - - - - - - - HW0 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW1 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW2 - Analog TRIM and hardware options - 0x0 - 0x20 - RW - - - - - - - - HW3 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW4 - not used yet - 0x0 - 0x20 - RW - - - - - - - - HW5 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW6 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW7 - reserved - 0x0 - 0x20 - RW - - - - - - - - PKH0 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH1 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH2 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH3 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH4 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH5 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH6 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH7 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - XK0 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK1 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK2 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK3 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK4 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK5 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK6 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK7 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK8 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK9 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK10 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK11 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK12 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK13 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK14 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK15 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK16 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK17 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK18 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK19 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK20 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK21 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK22 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK23 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK24 - RMA lock and relock passwords - 0x0 - 0x20 - RW - - - - - - - - XK25 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK26 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK27 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK28 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK29 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK30 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK31 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK32 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK33 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK34 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK35 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK36 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK37 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK38 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK39 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK40 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK41 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK42 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK43 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK44 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK45 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK46 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK47 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK48 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK49 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK50 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK51 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK52 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK53 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK54 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK55 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK56 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK57 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK58 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK59 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK60 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK61 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK62 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK63 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - ECC_USE - SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. - 0x4 - 0x4 - R - - - SAFMEM_SIZE - SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. - 0x0 - 0x4 - R - - - - - - - - MAJREV - IP Version major revision information. - 0x4 - 0x4 - R - - - MINREV - IP Version minor revision information. - 0x0 - 0x4 - R - - - - - - - - ID - IP Identification. - 0x0 - 0x20 - R - - - - - - - - ID - IP Magic Identification. - 0x0 - 0x20 - R - - - - - - - - - \ No newline at end of file diff --git a/lib/stlink/Data_Base/STM32_Prog_DB_0x501.xml b/lib/stlink/Data_Base/STM32_Prog_DB_0x501.xml deleted file mode 100644 index 2e866a6d..00000000 --- a/lib/stlink/Data_Base/STM32_Prog_DB_0x501.xml +++ /dev/null @@ -1,1820 +0,0 @@ - - - - 0x501 - STMicroelectronics - MPU - Cortex-A7 - STM32MP13xx - STM32MP - ARM 32-bit Cortex-A7 based device, CPU clock up to 600MHz - - - - - - - - - - - - - Embedded SRAM - Storage - - 0xFF - RWE - - - - - Single - - - - - - - - - OTP Memory - Configuration - - RW - - - - OTP - - - - - none - none - 0x0 - 0x20 - R - - - - - - - - TR - set SAFMEM Ring current level, default value = 0b00 - 0x7 - 0x2 - RW - - - PRGWIDTH - SAFMEM Programming Pulse Width, default value = 0b0001 - 0x3 - 0x4 - RW - - - FRC - SAFMEM CLOCK frequency range selection, default value = 0b11 - 0x1 - 0x2 - RW - - - PWRUP - SAFMEM Power up control - 0x0 - 0x1 - RW - - - - - - - - BIST2LOCK - 0: BIST2 is not locked, 1: BIST2 is locked. - 0x7 - 0x1 - R - - - BIST1LOCK - 0: BIST1 is not locked, 1: BIST1 is locked. - 0x6 - 0x1 - R - - - PWRON - 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. - 0x5 - 0x1 - R - - - PROGFAIL - 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. - 0x4 - 0x1 - R - - - BUSY - 0: SAFMEM is Idle, 1: SAFMEM operation is on going. - 0x3 - 0x1 - R - - - INVALID - 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. - 0x2 - 0x1 - R - - - FULLDBG - 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. - 0x1 - 0x1 - R - - - SECURE - 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. - 0x0 - 0x1 - R - - - - - - - - GPLOCK - 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. - 0x4 - 0x1 - RW - - - FENREG - 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. - 0x3 - 0x1 - RW - - - DENREG - 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. - 0x2 - 0x1 - RW - - - OTP - 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. - 0x0 - 0x1 - RW - - - - - - - - DBGSWENABLE - Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. - 0xA - 0x1 - RW - - - CFGSDISABLE - Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. - 0x9 - 0x1 - RW - - - CP15SDISABLE - Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. - 0x7 - 0x2 - RW - - - SPNIDEN - Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. - 0x6 - 0x1 - RW - - - SPIDEN - Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. - 0x5 - 0x1 - RW - - - HDPEN - Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. - 0x4 - 0x1 - RW - - - DEVICEEN - Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. - 0x3 - 0x1 - RW - - - NIDEN - Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. - 0x2 - 0x1 - RW - - - DBGEN - Debug enable with signal dbgen. 0: Disabled, 1: Enabled. - 0x1 - 0x1 - RW - - - DFTEN - DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. - 0x0 - 0x1 - RW - - - - - - - - CAN_disable - 0: CAN interface is enabled, 1: CAN interface is disabled. - 0x3 - 0x1 - RW - - - GPU_disable - 0: GPU enabled, 1: GPU disabled. - 0x2 - 0x1 - RW - - - Dual_A7_disable - 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. - 0x1 - 0x1 - RW - - - Crypto_disable - 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. - 0x0 - 0x1 - RW - - - - - - - - W_R conf - This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM - 0x0 - 0x1 - RW - - - - - - - - BSEC_OTP_DISTURBED0 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED1 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_DISTURBED2 - If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR0 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR1 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_ERROR2 - If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. - 0x0 - 0x20 - R - - - - - - - - BSEC_OTP_WRLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_WRLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK0 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK1 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SPLOCK2 - If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK0 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK1 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SWLOCK2 - If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK0 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK1 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - BSEC_OTP_SRLOCK2 - If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register - 0x0 - 0x20 - RW - - - - - - - - CFG0 - These bits determins the OTP mode encoding - 0x0 - 0x7 - RW - - - - - - - - fdis3 - Disable CAN - 0x3 - 0x1 - RW - - - fdis2 - Disable GPU - 0x2 - 0x1 - RW - - - fdis1 - Disable CPU1 - 0x1 - 0x1 - RW - - - fdis0 - Disable Crypto (license export) - 0x0 - 0x1 - RW - - - - - - - - rma_force - RMA force Bit - 0x0 - 0x1 - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - - - - - - CFG3 - These bits determins the BOOT source definition - 0x0 - 0x20 - RW - - - - - - - - CFG4 - These bits determins the BOOT monotonic counter - 0x0 - 0x20 - RW - - - - - - - - CFG5 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG6 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG7 - These bits determins the BOOT AFmux configuration - 0x0 - 0x20 - RW - - - - - - - - CFG8 - BOOT/Device configuration. - 0x2 - 0x1E - RW - - - rma_relock - RMA relock Bit - 0x1 - 0x1 - RW - - - rma_lock - RMA lock Bit - 0x0 - 0x1 - RW - - - - - - - - CFG9 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG10 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG11 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - CFG12 - These bits determin the device configuration. - 0x0 - 0x20 - RW - - - - - - - - ID0 - Lot ID on 42bit (11LSB's) - 0x15 - 0xB - RW - - - ID0 - Wafer ID - 0x10 - 0x5 - RW - - - ID0 - Wafer Y coordinates - 0x8 - 0x8 - RW - - - ID0 - Wafer X coordinates - 0x0 - 0x8 - RW - - - - - - - - ID1 - Lot ID on 42bit (31MSB's) - 0x0 - 0x20 - RW - - - - - - - - ID2 - Test program flow T[12],F[12],Q[12] - 0x14 - 0xC - RW - - - ID2 - FT program revision - 0xA - 0xA - RW - - - ID2 - EWS program revision - 0x0 - 0xA - RW - - - - - - - - HW0 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW1 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW2 - Analog TRIM and hardware options - 0x0 - 0x20 - RW - - - - - - - - HW3 - Analog TRIM - 0x0 - 0x20 - RW - - - - - - - - HW4 - not used yet - 0x0 - 0x20 - RW - - - - - - - - HW5 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW6 - memory repair bits - 0x0 - 0x20 - RW - - - - - - - - HW7 - reserved - 0x0 - 0x20 - RW - - - - - - - - PKH0 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH1 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH2 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH3 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH4 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH5 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH6 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - PKH7 - Public Key Hash - 0x0 - 0x20 - RW - - - - - - - - XK0 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK1 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK2 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK3 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK4 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK5 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK6 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK7 - ST ECDSA Private Key for SSP - 0x0 - 0x20 - RW - - - - - - - - XK8 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK9 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK10 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK11 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK12 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK13 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK14 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK15 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK16 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK17 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK18 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK19 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK20 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK21 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK22 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK23 - ST Public ECDSA Chip Certificate for SSP - 0x0 - 0x20 - RW - - - - - - - - XK24 - RMA lock and relock passwords - 0x0 - 0x20 - RW - - - - - - - - XK25 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK26 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK27 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK28 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK29 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK30 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK31 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK32 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK33 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK34 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK35 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK36 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK37 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK38 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK39 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK40 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK41 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK42 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK43 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK44 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK45 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK46 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK47 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK48 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK49 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK50 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK51 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK52 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK53 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK54 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK55 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK56 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK57 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK58 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK59 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK60 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK61 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK62 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - XK63 - OEM OTP secret word - 0x0 - 0x20 - RW - - - - - - - - ECC_USE - SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. - 0x4 - 0x4 - R - - - SAFMEM_SIZE - SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. - 0x0 - 0x4 - R - - - - - - - - MAJREV - IP Version major revision information. - 0x4 - 0x4 - R - - - MINREV - IP Version minor revision information. - 0x0 - 0x4 - R - - - - - - - - ID - IP Identification. - 0x0 - 0x20 - R - - - - - - - - ID - IP Magic Identification. - 0x0 - 0x20 - R - - - - - - - - - \ No newline at end of file