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Commits on May 28, 2026

• Merge branch 'code_cleanup'

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Commits on May 27, 2026

• Fix Mini V1/V2 bugs

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Commits on May 26, 2026

• tx_path_top: updated docs with lime_txpct_fifo module rework

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• Remove remaining platform name checks

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• Remove `hw_ver` from LMS7002Top; simplify init logic and signal assignments

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Commits on May 25, 2026

• Refactor LMS7002 control logic for simplification and remove `limesdr_mini` platform-specific handling

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• lime_txpct_fifo: removed ram attributes, they should by added with constraints if needed

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• Gateware clocking logic refactored

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Commits on May 21, 2026

• tx_path_top: fixed payload ram words calculation for lime_txpct_fifo

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• FT601: reduced FPGA->PC buffer size to fit two packets

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Commits on May 20, 2026

• wip

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Commits on May 18, 2026

• Revert "tx_path_top: added sync fifo before lime_txpct_fifo to cut timing path from sample padder tready"

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• tx_path_top: removed unnecessary logic ir txpct buffer

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• lime_txpct_fifo: improved timing with payload words remaining down counter

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Commits on May 15, 2026

• tx_path_top: added sync fifo before lime_txpct_fifo to cut timing path from sample padder tready

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• simple_dual_port_ram: removed synth attribute for xilinx

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Commits on May 14, 2026

• simple_dual_port_ram: changed default synthesis RAM_STYLE attribute

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• tx_path_top: fix constant value calculation

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• rx_path_top: fix for tx_pct_loss flag

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• tx_path_top: initial version for lime_txpct_fifo

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Commits on May 13, 2026

• simple_dual_port_ram: initial codebase

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• lime_txpct_fifo: initial codebase

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Commits on May 5, 2026

• Add GSAParser and RMCParser modules for NMEA parsing and change ZDAParser to LiteXModule

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Commits on May 4, 2026

• Update docs links

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Commits on Apr 29, 2026

• Add missing files

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Commits on Apr 27, 2026

• Update rx_path_top/tx_path_top documentation. Remove outdated docs

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Commits on Apr 22, 2026

• rx_path_top: moved timestap logic to helper modules

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• Add missing files

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Commits on Apr 21, 2026

• LimeDFB update

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Commits on Mar 25, 2026

• Refactor `m_axis_tvalid_reg` assignment to accommodate lack of vhdl2008 support in quartus.

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Commits on Mar 20, 2026

• afe79xx: updated docs with interpolate/decimate blocks

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Commits on Mar 5, 2026

• Merge remote-tracking branch 'origin/xilinx_decimate'

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• Prepare for merging

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Commits on Mar 4, 2026

• Fix constraints in afe79xx.py

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• added interpolate_4ch and decimate_4ch modules

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