This repository contains my practice work for learning and exploring Verilog using EDA Playground and HDLBits. Below is an index of the items included, each with a topic and serial number.
| Sr. No. | Topic | Description |
|---|---|---|
| 0 | Getting Started | Setting up and using EDA Playground |
| 1 | Basic Gates | AND, OR, NOT, NAND, NOR, XOR, XNOR |
| 3 | Half Adder | Half adder(AND and XOR gate used |
| 4 | Full Adder | Full adder(AND,OR and XOR gate used |
| 5 | Half & Full Subtractor | Half & Full Subtractor(AND,OR and XOR gate used |
| 6 | n bit Ripple carry Adder | Used Full Adder and Learn Module Instantiation In Verilog |
| 7 | 2:1,4:1 and 8:1 MUX | How to use 2:1 for 4:1 and 2:1 4:1 together for 8:1 |
| 8 | Code Converter | Binary to Gray , Gray to Binary |
| 9 | D-Flip FLop | Sequential CKT Using Gate and Behavioral modelling |
| 10 | T-Flip FLop | Sequential CKT Using Gate and Behavioral modelling |
| 11 | JK-Flip FLop | Sequential CKT Using Gate and Behavioral modelling |
| 12 | SR-Flip FLop | Sequential CKT Using Gate and Behavioral modelling |
| 13 | 7 Segment Display | a–g to represent digits 0–F |
| 14 | MOD 10 Counter | Using Gate and Behavioral modelling |
| 15 | 8_bit_ALU | Addition, subtraction, bitwise logic, shifts, and comparison |
| 16 | Seq_Detector 1011 | FSM Using Gate and Behavioral modelling |
| 17 | Seq_Detector 1101 | FSM Using Gate and Behavioral modelling |
- Introduction to EDA Playground
- Creating your first Verilog file
- Running simulations
- For simulation i used following :
- Selected Verilog/System Verilog on Design and TestBench in LANGUAGE & LIBRARIES dropdown.
- Selected Aldec Riviera Pro 2023.04 which automatically manage other things .
- Selected EPWave after Run (if you want to see wavefoerm ). - You can refer to my account EDA Profile and HDLBits Profile
2. Basic Gates
- Implementation of basic gates in Verilog
- Example codes for AND, OR, NOT, NAND, NOR, XOR, XNOR,
- For All Gates refer Logical Gates
- Implementation of Half Adder using AND and XOR gate.
- Example code are in 3.Practice here.
- For more details on Half Adder you can refer to GFG Link
- Implementation of Full Adder using AND,OR and XOR gate.
- Example code are in 4.Full_Adder here.
- For more details on Full Adder you can refer to GFG Link
- Implementation of Half and Full Subtractor using AND,OR and XOR gate.
- Example code are in 5.Half Subtractor && Full Subtractor here.
- For more details on Full Subtractor you can refer to GFG Link and for Half Subtractor GFG Link
- Implementation of 4-bit Ripple Carry adder using 4-Full Adder.
- New Learning How to Module Instantiation In Verilog and how we need to tackle things in case of EDA PLAYGROUND where get know about the $dumpvars.
- For more info on Ripple Carry Adder click here and for Module Instantiation click here
- Implementation of 2:1 ,4:1 using 2:1 and without using 2:1 ,8:1 using 4:1 and 2:1.
- New Learning How to Module Instantiation In Verilog and how we need to tackle things in case of EDA PLAYGROUND where get know about the $dumpvars. I used it as $dumpvars(1) for 2:1 and 4:1 and for 8:1.
- For more info on Multiplexer click here
- Implementation of Gray to Binary Converter using simplified Boolean logic:
- B2 = G2
- B1 = G1 ⊕ G2
- B0 = G0 ⊕ G1 ⊕ G2
- Implementation of Binary to Gray Converter using simplified Boolean logic:
- G2 = B2
- G1 = B1 ⊕ B2
- G0 = B0 ⊕ B1
- New Learning Explored how to derive conversion logic using Karnaugh Maps and Boolean simplification. Practiced module instantiation in Verilog for clean hierarchy and reusability.
- Tackled simulation setup in EDA PLAYGROUND, especially for waveform visibility:
- Used
$dumpvars(1)for compact modules and$dumpvars(0)for top-level testbenches. - Ensured
$dumpfile("gray_to_binary.vcd")was declared before simulation begins.
- Used
- For more info on Gray Code and Binary Conversion click here
- A D flip-flop stores the input value (
D) on a clock edge and holds it stable until the next trigger. - It’s edge-sensitive, meaning it reacts only on rising or falling clock transitions, making it ideal for synchronized data storage.
- Widely used in registers, counters, and memory elements, it forms the backbone of sequential digital circuits.
- For more info on Modelling in Verilog click here
10. T Flip Flop
- A T (Toggle) flip-flop changes its output state on every clock edge when the input
Tis high (1). - When
T = 0, it holds its previous state, making it ideal for frequency division and binary counting. - It’s derived from the JK flip-flop by tying both inputs together (
J = K = T). - Commonly used in ripple counters and clock dividers for sequential timing control.
- For more info on Modelling in Verilog click here
11. JK Flip Flop
- A JK flip-flop is a versatile sequential element that resolves the invalid state of the SR flip-flop.
- When
J = 1, K = 1, it toggles the output; otherwise, it behaves like an SR flip-flop. - It’s edge-triggered and highly flexible, making it suitable for counters, shift registers, and control units.
- Often used in synchronous systems where controlled toggling and state transitions are required.
- For more info on Modelling in Verilog click here
12. SR Flip Flop
- An SR (Set-Reset) flip-flop sets or resets its output based on the inputs
SandRduring a clock edge. S = 1, R = 0sets the output;S = 0, R = 1resets it;S = R = 0holds the state;S = R = 1is invalid.- It’s one of the simplest memory elements, useful for basic control logic and latching mechanisms.
- Often used in debouncing circuits and simple state machines.
- For more info on Modelling in Verilog click here
- A 7-segment display decoder converts a 4-bit hexadecimal input into a 7-bit output that lights up segments
a–gto represent digits0–F. - It maps binary values to visual patterns, enabling human-readable output on embedded systems and digital devices.
- Commonly used in digital clocks, calculators, counters, and embedded interfaces.
- Ideal for beginners learning combinational logic and display interfacing.
- For more info on Modelling in Verilog click here
14. MOD 10 Counter
- A MOD-10 counter cycles through 10 states (
0000to1001) before resetting to0000, effectively counting from0to9. - It uses synchronous logic and flip-flops to increment on each clock edge, resetting after the 10th count.
- Widely used in digital clocks, frequency dividers, and decimal counting systems.
- A great example of sequential logic and state-based design in Verilog.
- For more info on Modelling in Verilog click here
15. 8-bit ALU
- An 8-bit ALU performs arithmetic and logic operations on two 8-bit inputs, including addition, subtraction, bitwise logic, shifts, and comparison.
- Designed using combinational logic with a 3-bit control signal to select the operation.
- Includes a
Zeroflag output for condition checking, useful in control flow and branching. - Ideal for showcasing modular design, opcode mapping, and waveform-based verification.
- For more on ALU design in Verilog click here
- A Mealy-style FSM that detects the binary sequence
1011in a serial input stream. - Uses 5 states to track progress and asserts output immediately upon detection.
- Demonstrates state transitions, pattern recognition, and non-overlapping detection.
- Useful in control systems, protocol monitoring, and digital communication.
- For FSM modeling techniques in Verilog click here
- A Mealy FSM designed to detect the sequence
1101using 5 distinct states. - Output is asserted as soon as the final bit of the sequence is received.
- Highlights sequential logic, state encoding, and real-time pattern detection.
- Commonly used in serial data analyzers, bitstream filters, and control logic.
- For FSM design examples in Verilog click here
Feel free to add more topics or update this README as you progress in your Verilog learning journey!