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author
Morten Borup Petersen
committed
Works!
1 parent 2dbba53 commit 758203c

17 files changed

+76
-80
lines changed

‎external/VSRTL

‎external/fancytabbar/CMakeLists.txt

+3-3
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,10 @@ set(CMAKE_INCLUDE_CURRENT_DIR ON)
88
set(CMAKE_AUTOUIC ON)
99
set(CMAKE_AUTORCC ON)
1010

11-
file(GLOB LIB_SOURCES src/*.cpp)
12-
file(GLOB LIB_HEADERS include/fancytabbar/*.h)
11+
file(GLOB LIB_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/src/*.cpp)
12+
file(GLOB LIB_HEADERS ${CMAKE_CURRENT_SOURCE_DIR}/include/fancytabbar/*.h)
1313

14-
add_library(fancytabbar STATIC ${LIB_SOURCES})
14+
add_library(fancytabbar STATIC ${LIB_SOURCES} ${LIB_HEADERS})
1515
add_library(fancytabbar::fancytabbar ALIAS fancytabbar)
1616
target_link_libraries(fancytabbar Qt6::Core Qt6::Widgets)
1717
target_include_directories(fancytabbar PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include)

‎src/processors/RISC-V/riscv.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ enum class ALUOp {
141141
REMW,
142142
REMUW
143143
};
144-
enum class RegWrSrc { MEMREAD, ALURES, PC4, N };
144+
enum class RegWrSrc { MEMREAD, ALURES, PC4 };
145145
enum class AluSrc1 { REG1, PC };
146146
enum class AluSrc2 { REG2, IMM };
147147
enum class CompOp { NOP, EQ, NE, LT, LTU, GE, GEU };

‎src/processors/RISC-V/rv5s/rv5s_idex.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ class RV5S_IDEX : public IDEX<XLEN> {
3434

3535
REGISTERED_CLEN_INPUT(rd_reg1_idx, c_RVRegsBits);
3636
REGISTERED_CLEN_INPUT(rd_reg2_idx, c_RVRegsBits);
37-
REGISTERED_CLEN_INPUT(opcode, ceillog2(magic_enum::enum_count<RVInstr>()));
37+
REGISTERED_CLEN_INPUT(opcode, enumBitWidth<RVInstr>());
3838

3939
REGISTERED_CLEN_INPUT(stalled, 1);
4040
};

‎src/processors/RISC-V/rv5s_no_fw/rv5s_no_fw_idex.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ class RV5S_NO_FW_IDEX : public IDEX<XLEN> {
2929
CONNECT_REGISTERED_CLEN_INPUT(stalled, 0, 1);
3030
}
3131

32-
REGISTERED_CLEN_INPUT(opcode, ceillog2(magic_enum::enum_count<RVInstr>()));
32+
REGISTERED_CLEN_INPUT(opcode, enumBitWidth<RVInstr>());
3333
REGISTERED_CLEN_INPUT(stalled, 1);
3434
};
3535

‎src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_exmem.h

+3-4
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
#include "VSRTL/core/vsrtl_component.h"
44
#include "VSRTL/core/vsrtl_register.h"
55

6-
#include "processors/RISC-V/riscv.h"
6+
#include "../riscv.h"
77

88
namespace vsrtl {
99
namespace core {
@@ -37,13 +37,12 @@ class EXMEM : public Component {
3737
REGISTERED_CLEN_INPUT(r2, XLEN);
3838

3939
// Control
40-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl,
41-
ceillog2(magic_enum::enum_count<RegWrSrc>()));
40+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl, enumBitWidth<RegWrSrc>());
4241
REGISTERED_CLEN_INPUT(wr_reg_idx, c_RVRegsBits);
4342
REGISTERED_CLEN_INPUT(reg_do_write, 1);
4443
REGISTERED_CLEN_INPUT(mem_do_write, 1);
4544
REGISTERED_CLEN_INPUT(mem_do_read, 1);
46-
REGISTERED_CLEN_INPUT(mem_op, ceillog2(magic_enum::enum_count<MemOp>()));
45+
REGISTERED_CLEN_INPUT(mem_op, enumBitWidth<MemOp>());
4746

4847
// Register bank controls
4948
INPUTPORT(enable, 1);

‎src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_idex.h

+6-9
Original file line numberDiff line numberDiff line change
@@ -45,19 +45,16 @@ class IDEX : public Component {
4545
REGISTERED_CLEN_INPUT(imm, XLEN);
4646

4747
// Control
48-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl,
49-
ceillog2(magic_enum::enum_count<RegWrSrc>()));
48+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl, enumBitWidth<RegWrSrc>());
5049
REGISTERED_CLEN_INPUT(wr_reg_idx, c_RVRegsBits);
5150
REGISTERED_CLEN_INPUT(reg_do_write, 1);
52-
REGISTERED_CLEN_INPUT(alu_op1_ctrl,
53-
ceillog2(magic_enum::enum_count<AluSrc1>()));
54-
REGISTERED_CLEN_INPUT(alu_op2_ctrl,
55-
ceillog2(magic_enum::enum_count<AluSrc2>()));
56-
REGISTERED_CLEN_INPUT(alu_ctrl, ceillog2(magic_enum::enum_count<ALUOp>()));
51+
REGISTERED_CLEN_INPUT(alu_op1_ctrl, enumBitWidth<AluSrc1>());
52+
REGISTERED_CLEN_INPUT(alu_op2_ctrl, enumBitWidth<AluSrc2>());
53+
REGISTERED_CLEN_INPUT(alu_ctrl, enumBitWidth<ALUOp>());
5754
REGISTERED_CLEN_INPUT(mem_do_write, 1);
5855
REGISTERED_CLEN_INPUT(mem_do_read, 1);
59-
REGISTERED_CLEN_INPUT(mem_op, ceillog2(magic_enum::enum_count<MemOp>()));
60-
REGISTERED_CLEN_INPUT(br_op, ceillog2(magic_enum::enum_count<CompOp>()));
56+
REGISTERED_CLEN_INPUT(mem_op, enumBitWidth<MemOp>());
57+
REGISTERED_CLEN_INPUT(br_op, enumBitWidth<CompOp>());
6158
REGISTERED_CLEN_INPUT(do_br, 1);
6259
REGISTERED_CLEN_INPUT(do_jmp, 1);
6360

‎src/processors/RISC-V/rv5s_no_fw_hz/rv5s_no_fw_hz_memwb.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,7 @@ class MEMWB : public Component {
3434
REGISTERED_INPUT(mem_read, XLEN);
3535

3636
// Control
37-
REGISTERED_INPUT(reg_wr_src_ctrl,
38-
ceillog2(magic_enum::enum_count<RegWrSrc>()));
37+
REGISTERED_INPUT(reg_wr_src_ctrl, enumBitWidth<RegWrSrc>());
3938
REGISTERED_INPUT(wr_reg_idx, c_RVRegsBits);
4039
REGISTERED_INPUT(reg_do_write, 1);
4140

‎src/processors/RISC-V/rv6s_dual/rv6s_dual.h

+2-4
Original file line numberDiff line numberDiff line change
@@ -567,8 +567,7 @@ class RV6S_DUAL : public RipesVSRTLProcessor {
567567

568568
SUBCOMPONENT(data_way_pc, TYPE(EnumMultiplexer<WaySrc, XLEN>));
569569
SUBCOMPONENT(data_way_opcode,
570-
TYPE(EnumMultiplexer<
571-
WaySrc, ceillog2(magic_enum::enum_count<RVInstr>())>));
570+
TYPE(EnumMultiplexer<WaySrc, enumBitWidth<RVInstr>()>));
572571
SUBCOMPONENT(data_way_instr, TYPE(EnumMultiplexer<WaySrc, c_RVInstrWidth>));
573572
SUBCOMPONENT(data_way_wr_reg_idx,
574573
TYPE(EnumMultiplexer<WaySrc, c_RVRegsBits>));
@@ -579,8 +578,7 @@ class RV6S_DUAL : public RipesVSRTLProcessor {
579578

580579
SUBCOMPONENT(exec_way_pc, TYPE(EnumMultiplexer<WaySrc, XLEN>));
581580
SUBCOMPONENT(exec_way_opcode,
582-
TYPE(EnumMultiplexer<
583-
WaySrc, ceillog2(magic_enum::enum_count<RVInstr>())>));
581+
TYPE(EnumMultiplexer<WaySrc, enumBitWidth<RVInstr>()>));
584582
SUBCOMPONENT(exec_way_instr, TYPE(EnumMultiplexer<WaySrc, c_RVInstrWidth>));
585583
SUBCOMPONENT(exec_way_wr_reg_idx,
586584
TYPE(EnumMultiplexer<WaySrc, c_RVRegsBits>));

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_control.h

+32-25
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ namespace core {
99
using namespace Ripes;
1010

1111
class Control_DUAL : public Component {
12-
static RegWrSrcDual do_reg_wr_src_ctrl_dual(const VSRTL_VT_U &opc) {
13-
switch (magic_enum::enum_value<RVInstr>(opc)) {
12+
static RegWrSrcDual do_reg_wr_src_ctrl_dual(RVInstr opc) {
13+
switch (opc) {
1414
// Jump instructions
1515
case RVInstr::JALR:
1616
case RVInstr::JAL:
@@ -21,7 +21,7 @@ class Control_DUAL : public Component {
2121
}
2222
}
2323

24-
static RegWrSrcDataDual do_reg_wr_src_ctrl_data(const VSRTL_VT_U &opc) {
24+
static RegWrSrcDataDual do_reg_wr_src_ctrl_data(RVInstr opc) {
2525
if (Control::do_mem_ctrl(opc) != MemOp::NOP) {
2626
return RegWrSrcDataDual::MEM;
2727
} else {
@@ -33,65 +33,72 @@ class Control_DUAL : public Component {
3333
Control_DUAL(const std::string &name, SimComponent *parent)
3434
: Component(name, parent) {
3535
comp_ctrl << [=] {
36-
return exec_valid.uValue() ? Control::do_comp_ctrl(opcode_exec.uValue())
37-
: CompOp::NOP;
36+
return exec_valid.uValue()
37+
? Control::do_comp_ctrl(opcode_exec.eValue<RVInstr>())
38+
: CompOp::NOP;
3839
};
3940
do_branch << [=] {
40-
return exec_valid.uValue() ? Control::do_branch_ctrl(opcode_exec.uValue())
41-
: 0;
41+
return exec_valid.uValue()
42+
? Control::do_branch_ctrl(opcode_exec.eValue<RVInstr>())
43+
: 0;
4244
};
4345
do_jump << [=] {
44-
return exec_valid.uValue() ? Control::do_jump_ctrl(opcode_exec.uValue())
45-
: 0;
46+
return exec_valid.uValue()
47+
? Control::do_jump_ctrl(opcode_exec.eValue<RVInstr>())
48+
: 0;
4649
};
4750
mem_ctrl << [=] {
48-
return data_valid.uValue() ? Control::do_mem_ctrl(opcode_data.uValue())
49-
: MemOp::NOP;
51+
return data_valid.uValue()
52+
? Control::do_mem_ctrl(opcode_data.eValue<RVInstr>())
53+
: MemOp::NOP;
5054
};
5155

5256
reg_do_write_ctrl_exec << [=] {
5357
return exec_valid.uValue() &&
54-
Control::do_reg_do_write_ctrl(opcode_exec.uValue());
58+
Control::do_reg_do_write_ctrl(opcode_exec.eValue<RVInstr>());
5559
};
5660
reg_do_write_ctrl_data << [=] {
5761
return data_valid.uValue() &&
58-
Control::do_reg_do_write_ctrl(opcode_data.uValue());
62+
Control::do_reg_do_write_ctrl(opcode_data.eValue<RVInstr>());
5963
};
6064

6165
reg_wr_src_ctrl <<
62-
[=] { return do_reg_wr_src_ctrl_dual(opcode_exec.uValue()); };
66+
[=] { return do_reg_wr_src_ctrl_dual(opcode_exec.eValue<RVInstr>()); };
6367
reg_wr_src_data_ctrl <<
64-
[=] { return do_reg_wr_src_ctrl_data(opcode_data.uValue()); };
68+
[=] { return do_reg_wr_src_ctrl_data(opcode_data.eValue<RVInstr>()); };
6569

6670
alu_op1_ctrl_exec << [=] {
6771
return exec_valid.uValue()
68-
? Control::do_alu_op1_ctrl(opcode_exec.uValue())
72+
? Control::do_alu_op1_ctrl(opcode_exec.eValue<RVInstr>())
6973
: AluSrc1::REG1;
7074
};
7175
alu_op2_ctrl_exec << [=] {
7276
return exec_valid.uValue()
73-
? Control::do_alu_op2_ctrl(opcode_exec.uValue())
77+
? Control::do_alu_op2_ctrl(opcode_exec.eValue<RVInstr>())
7478
: AluSrc2::REG2;
7579
};
7680
alu_ctrl_exec << [=] {
77-
return exec_valid.uValue() ? Control::do_alu_ctrl(opcode_exec.uValue())
78-
: ALUOp::NOP;
81+
return exec_valid.uValue()
82+
? Control::do_alu_ctrl(opcode_exec.eValue<RVInstr>())
83+
: ALUOp::NOP;
7984
};
8085

8186
alu_op2_ctrl_data << [=] {
8287
return data_valid.uValue()
83-
? Control::do_alu_op2_ctrl(opcode_data.uValue())
88+
? Control::do_alu_op2_ctrl(opcode_data.eValue<RVInstr>())
8489
: AluSrc2::REG2;
8590
};
8691
alu_ctrl_data << [=] {
87-
return data_valid.uValue() ? Control::do_alu_ctrl(opcode_data.uValue())
88-
: ALUOp::NOP;
92+
return data_valid.uValue()
93+
? Control::do_alu_ctrl(opcode_data.eValue<RVInstr>())
94+
: ALUOp::NOP;
8995
};
9096

91-
mem_do_write_ctrl <<
92-
[=] { return Control::do_do_mem_write_ctrl(opcode_data.uValue()); };
97+
mem_do_write_ctrl << [=] {
98+
return Control::do_do_mem_write_ctrl(opcode_data.eValue<RVInstr>());
99+
};
93100
mem_do_read_ctrl <<
94-
[=] { return Control::do_do_read_ctrl(opcode_data.uValue()); };
101+
[=] { return Control::do_do_read_ctrl(opcode_data.eValue<RVInstr>()); };
95102
}
96103

97104
INPUTPORT_ENUM(opcode_exec, RVInstr);

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_exmem.h

+2-4
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,8 @@ class RV5S_EXMEM_DUAL : public RV5S_EXMEM<XLEN> {
2626

2727
REGISTERED_CLEN_INPUT(wr_reg_idx_data, c_RVRegsBits);
2828
REGISTERED_CLEN_INPUT(reg_do_write_data, 1);
29-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_dual,
30-
ceillog2(magic_enum::enum_count<RegWrSrcDual>()));
31-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_data,
32-
ceillog2(magic_enum::enum_count<RegWrSrcDataDual>()));
29+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_dual, enumBitWidth<RegWrSrcDual>());
30+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_data, enumBitWidth<RegWrSrcDataDual>());
3331
REGISTERED_CLEN_INPUT(pc_data, XLEN);
3432

3533
REGISTERED_CLEN_INPUT(alures_data, XLEN);

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_forwardingunit.h

+8-3
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,13 @@
55
#include "VSRTL/core/vsrtl_component.h"
66

77
namespace Ripes {
8-
Enum(ForwardingSrcDual, IdStage, MemStageExec, MemStageMem, WbStageExec,
9-
WbStageMem);
8+
enum class ForwardingSrcDual {
9+
IdStage,
10+
MemStageExec,
11+
MemStageMem,
12+
WbStageExec,
13+
WbStageMem
14+
};
1015
}
1116

1217
namespace vsrtl {
@@ -22,7 +27,7 @@ class ForwardingUnit_DUAL : public Component {
2227
return ForwardingSrcDual::MemStageExec;
2328
} else if (readidx == mem_reg_wr_idx_data.uValue() &&
2429
mem_reg_wr_en_data.uValue() &&
25-
mem_reg_mem_op.uValue() == MemOp::NOP) {
30+
mem_reg_mem_op.eValue<MemOp>() == MemOp::NOP) {
2631
return ForwardingSrcDual::MemStageMem;
2732
} else if (readidx == wb_reg_wr_idx_exec.uValue() &&
2833
wb_reg_wr_en_exec.uValue()) {

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_hazardunit.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ class HazardUnit_DUAL : public Component {
7676
// register file must be performed before handling the ecall. Hence, the
7777
// front-end of the pipeline shall be stalled until the remainder of the
7878
// pipeline has been cleared and there are no more outstanding writes.
79-
const bool isEcall = opcode.uValue() == RVInstr::ECALL;
79+
const bool isEcall = opcode.eValue<RVInstr>() == RVInstr::ECALL;
8080
return isEcall &&
8181
(mem_do_reg_write_exec.uValue() || mem_do_reg_write_data.uValue() ||
8282
wb_do_reg_write_data.uValue() || wb_do_reg_write_exec.uValue());

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_idii.h

+2-4
Original file line numberDiff line numberDiff line change
@@ -58,14 +58,12 @@ class RV5S_IDII_DUAL : public Component {
5858

5959
REGISTERED_CLEN_INPUT(rd_reg1_idx_exec, c_RVRegsBits);
6060
REGISTERED_CLEN_INPUT(rd_reg2_idx_exec, c_RVRegsBits);
61-
REGISTERED_CLEN_INPUT(opcode_exec,
62-
ceillog2(magic_enum::enum_count<RVInstr>()));
61+
REGISTERED_CLEN_INPUT(opcode_exec, enumBitWidth<RVInstr>());
6362
REGISTERED_CLEN_INPUT(wr_reg_idx_exec, c_RVRegsBits);
6463

6564
REGISTERED_CLEN_INPUT(rd_reg1_idx_data, c_RVRegsBits);
6665
REGISTERED_CLEN_INPUT(rd_reg2_idx_data, c_RVRegsBits);
67-
REGISTERED_CLEN_INPUT(opcode_data,
68-
ceillog2(magic_enum::enum_count<RVInstr>()));
66+
REGISTERED_CLEN_INPUT(opcode_data, enumBitWidth<RVInstr>());
6967
REGISTERED_CLEN_INPUT(wr_reg_idx_data, c_RVRegsBits);
7068

7169
REGISTERED_CLEN_INPUT(way_stall, 1);

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_iiex.h

+4-8
Original file line numberDiff line numberDiff line change
@@ -47,17 +47,13 @@ class RV5S_IIEX_DUAL : public RV5S_IDEX<XLEN> {
4747

4848
REGISTERED_CLEN_INPUT(wr_reg_idx_data, c_RVRegsBits);
4949
REGISTERED_CLEN_INPUT(reg_do_write_data, 1);
50-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_dual,
51-
ceillog2(magic_enum::enum_count<RegWrSrcDual>()));
52-
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_data,
53-
ceillog2(magic_enum::enum_count<RegWrSrcDataDual>()));
50+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_dual, enumBitWidth<RegWrSrcDual>());
51+
REGISTERED_CLEN_INPUT(reg_wr_src_ctrl_data, enumBitWidth<RegWrSrcDataDual>());
5452

5553
REGISTERED_CLEN_INPUT(imm_data, XLEN);
5654

57-
REGISTERED_CLEN_INPUT(alu_op2_ctrl_data,
58-
ceillog2(magic_enum::enum_count<AluSrc2>()));
59-
REGISTERED_CLEN_INPUT(alu_ctrl_data,
60-
ceillog2(magic_enum::enum_count<ALUOp>()));
55+
REGISTERED_CLEN_INPUT(alu_op2_ctrl_data, enumBitWidth<AluSrc2>());
56+
REGISTERED_CLEN_INPUT(alu_ctrl_data, enumBitWidth<ALUOp>());
6157

6258
REGISTERED_CLEN_INPUT(exec_valid, 1);
6359
REGISTERED_CLEN_INPUT(data_valid, 1);

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_memwb.h

+2-4
Original file line numberDiff line numberDiff line change
@@ -26,10 +26,8 @@ class RV5S_MEMWB_DUAL : public RV5S_MEMWB<XLEN> {
2626

2727
REGISTERED_INPUT(wr_reg_idx_data, c_RVRegsBits);
2828
REGISTERED_INPUT(reg_do_write_data, 1);
29-
REGISTERED_INPUT(reg_wr_src_ctrl_dual,
30-
ceillog2(magic_enum::enum_count<RegWrSrcDual>()));
31-
REGISTERED_INPUT(reg_wr_src_ctrl_data,
32-
ceillog2(magic_enum::enum_count<RegWrSrcDataDual>()));
29+
REGISTERED_INPUT(reg_wr_src_ctrl_dual, enumBitWidth<RegWrSrcDual>());
30+
REGISTERED_INPUT(reg_wr_src_ctrl_data, enumBitWidth<RegWrSrcDataDual>());
3331
REGISTERED_INPUT(pc_data, XLEN);
3432
REGISTERED_INPUT(alures_data, XLEN);
3533

‎src/processors/RISC-V/rv6s_dual/rv6s_dual_waycontrol.h

+6-5
Original file line numberDiff line numberDiff line change
@@ -87,19 +87,20 @@ class WayControl : public Component {
8787
return hazard_1 || hazard_2;
8888
}
8989

90-
WayClass instrType(const VSRTL_VT_U opcode) const {
90+
WayClass instrType(RVInstr opcode) const {
9191
if (isLoadStore(opcode)) {
9292
return WayClass ::Data;
9393
} else if (isControlflow(opcode)) {
9494
return WayClass::Controlflow;
9595
} else if (opcode == RVInstr::ECALL) {
9696
return WayClass::Ecall;
97+
} else {
98+
return WayClass::Arithmetic;
9799
}
98-
return WayClass::Arithmetic;
99100
}
100101

101102
WaySrc otherWay(const WaySrc way) const {
102-
return way == +WaySrc::WAY1 ? WaySrc::WAY2 : WaySrc::WAY1;
103+
return way == WaySrc::WAY1 ? WaySrc::WAY2 : WaySrc::WAY1;
103104
}
104105

105106
/**
@@ -112,8 +113,8 @@ class WayControl : public Component {
112113
return;
113114

114115
// Default assignments
115-
const WayClass way1Type = instrType(opcode_way1.uValue());
116-
const WayClass way2Type = instrType(opcode_way2.uValue());
116+
const WayClass way1Type = instrType(opcode_way1.eValue<RVInstr>());
117+
const WayClass way2Type = instrType(opcode_way2.eValue<RVInstr>());
117118

118119
const bool stallNow = stall_in.uValue();
119120
if (stallNow) {

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