From c28b017f945eafbe1a4292b47a1cff830a95731b Mon Sep 17 00:00:00 2001
From: modm update bot <bot@modm.io>
Date: Tue, 13 Feb 2024 07:31:40 +0000
Subject: [PATCH] Update STM32 SVD files

---
 README.md             |  4 ++--
 stm32f4/STM32F401.svd |  4 ++--
 stm32f4/STM32F405.svd |  4 ++--
 stm32f4/STM32F407.svd |  4 ++--
 stm32f4/STM32F410.svd |  4 ++--
 stm32f4/STM32F411.svd |  4 ++--
 stm32f4/STM32F412.svd |  4 ++--
 stm32f4/STM32F413.svd |  4 ++--
 stm32f4/STM32F415.svd | 22 ++--------------------
 stm32f4/STM32F417.svd | 22 ++--------------------
 stm32f4/STM32F423.svd |  4 ++--
 stm32f4/STM32F427.svd | 22 ++++++++++++++++++----
 stm32f4/STM32F429.svd | 22 ++++++++++++++++++----
 stm32f4/STM32F437.svd | 22 ++++++++++++++++++----
 stm32f4/STM32F439.svd | 22 ++++++++++++++++++----
 stm32f4/STM32F446.svd |  4 ++--
 stm32f4/STM32F469.svd |  4 ++--
 stm32f4/STM32F479.svd |  4 ++--
 stm32g0/STM32G030.svd |  4 ++--
 stm32g0/STM32G031.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G041.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G050.svd |  4 ++--
 stm32g0/STM32G051.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G061.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G070.svd |  4 ++--
 stm32g0/STM32G071.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G081.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G0B0.svd |  4 ++--
 stm32g0/STM32G0B1.svd | 26 ++++++++++++++++++++++----
 stm32g0/STM32G0C1.svd | 26 ++++++++++++++++++++++----
 30 files changed, 284 insertions(+), 120 deletions(-)

diff --git a/README.md b/README.md
index a20b850..e019c39 100644
--- a/README.md
+++ b/README.md
@@ -14,9 +14,9 @@ Here is the list of the SVD file versions for each STM32 family:
 - STM32F1: v1.2
 - STM32F2: v1.2
 - STM32F3: v1.3
-- STM32F4: v1.9
+- STM32F4: v2.0
 - STM32F7: v1.0
-- STM32G0: v1.5
+- STM32G0: v1.6
 - STM32G4: v2.2
 - STM32H5: v1.1
 - STM32H7: v1.9
diff --git a/stm32f4/STM32F401.svd b/stm32f4/STM32F401.svd
index e85b692..3a8a5f1 100644
--- a/stm32f4/STM32F401.svd
+++ b/stm32f4/STM32F401.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F401</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32F401</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F405.svd b/stm32f4/STM32F405.svd
index 4a82a9d..5ae13cb 100644
--- a/stm32f4/STM32F405.svd
+++ b/stm32f4/STM32F405.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F405</name>
-  <version>1.6</version>
+  <version>1.7</version>
   <description>STM32F405</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F407.svd b/stm32f4/STM32F407.svd
index 16079db..1090c70 100644
--- a/stm32f4/STM32F407.svd
+++ b/stm32f4/STM32F407.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F407</name>
-  <version>1.6</version>
+  <version>1.7</version>
   <description>STM32F407</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F410.svd b/stm32f4/STM32F410.svd
index 7c24a52..42aebbe 100644
--- a/stm32f4/STM32F410.svd
+++ b/stm32f4/STM32F410.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F410</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32F410</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F411.svd b/stm32f4/STM32F411.svd
index fc6361d..1998e0c 100644
--- a/stm32f4/STM32F411.svd
+++ b/stm32f4/STM32F411.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F411</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32F411</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F412.svd b/stm32f4/STM32F412.svd
index af7039b..04ed39b 100644
--- a/stm32f4/STM32F412.svd
+++ b/stm32f4/STM32F412.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -18,7 +18,7 @@ Copyright (c) 2023 STMicroelectronics.
 -->
 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
    <name>STM32F412</name>
-   <version>1.6</version>
+   <version>1.7</version>
    <description>STM32F412</description>
    <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F413.svd b/stm32f4/STM32F413.svd
index 2a654a3..07c22d6 100644
--- a/stm32f4/STM32F413.svd
+++ b/stm32f4/STM32F413.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F413</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32F413</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F415.svd b/stm32f4/STM32F415.svd
index 6f3595d..89446b1 100644
--- a/stm32f4/STM32F415.svd
+++ b/stm32f4/STM32F415.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F415</name>
-  <version>1.2</version>
+  <version>1.3</version>
   <description>STM32F415</description>
   <cpu>
     <name>CM4</name>
@@ -47380,24 +47380,6 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
             </field>
           </fields>
         </register>
-        <register>
-          <name>OPTCR1</name>
-          <displayName>OPTCR1</displayName>
-          <description>Flash option control register
-          1</description>
-          <addressOffset>0x18</addressOffset>
-          <size>0x20</size>
-          <access>read-write</access>
-          <resetValue>0x0FFF0000</resetValue>
-          <fields>
-            <field>
-              <name>nWRP</name>
-              <description>Not write protect</description>
-              <bitOffset>16</bitOffset>
-              <bitWidth>12</bitWidth>
-            </field>
-          </fields>
-        </register>
       </registers>
     </peripheral>
     <peripheral>
diff --git a/stm32f4/STM32F417.svd b/stm32f4/STM32F417.svd
index d02aa53..145b4e0 100644
--- a/stm32f4/STM32F417.svd
+++ b/stm32f4/STM32F417.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F417</name>
-  <version>1.2</version>
+  <version>1.3</version>
   <description>STM32F417</description>
   <cpu>
     <name>CM4</name>
@@ -47335,24 +47335,6 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
             </field>
           </fields>
         </register>
-        <register>
-          <name>OPTCR1</name>
-          <displayName>OPTCR1</displayName>
-          <description>Flash option control register
-          1</description>
-          <addressOffset>0x18</addressOffset>
-          <size>0x20</size>
-          <access>read-write</access>
-          <resetValue>0x0FFF0000</resetValue>
-          <fields>
-            <field>
-              <name>nWRP</name>
-              <description>Not write protect</description>
-              <bitOffset>16</bitOffset>
-              <bitWidth>12</bitWidth>
-            </field>
-          </fields>
-        </register>
       </registers>
     </peripheral>
     <peripheral>
diff --git a/stm32f4/STM32F423.svd b/stm32f4/STM32F423.svd
index 081bb8e..a72b241 100644
--- a/stm32f4/STM32F423.svd
+++ b/stm32f4/STM32F423.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F423</name>
-  <version>1.1</version>
+  <version>1.2</version>
   <description>STM32F423</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F427.svd b/stm32f4/STM32F427.svd
index 0373083..a39c6b6 100644
--- a/stm32f4/STM32F427.svd
+++ b/stm32f4/STM32F427.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F427</name>
-  <version>1.6</version>
+  <version>1.7</version>
   <description>STM32F427</description>
   <cpu>
     <name>CM4</name>
@@ -9727,6 +9727,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
           <size>0x20</size>
           <resetValue>0x00000083</resetValue>
           <fields>
+            <field>
+              <name>PLLSAIRDY</name>
+              <description>PLLSAI clock ready flag</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLSAION</name>
+              <description>PLLSAI enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
             <field>
               <name>PLLI2SRDY</name>
               <description>PLLI2S clock ready flag</description>
@@ -11123,13 +11137,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI5ENR</name>
+              <name>SPI5EN</name>
               <description>SPI5 clock enable</description>
               <bitOffset>20</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI6ENR</name>
+              <name>SPI6EN</name>
               <description>SPI6 clock enable</description>
               <bitOffset>21</bitOffset>
               <bitWidth>1</bitWidth>
diff --git a/stm32f4/STM32F429.svd b/stm32f4/STM32F429.svd
index 1048ed3..a10fa3f 100644
--- a/stm32f4/STM32F429.svd
+++ b/stm32f4/STM32F429.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F429</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32F429</description>
   <cpu>
     <name>CM4</name>
@@ -9727,6 +9727,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
           <size>0x20</size>
           <resetValue>0x00000083</resetValue>
           <fields>
+            <field>
+              <name>PLLSAIRDY</name>
+              <description>PLLSAI clock ready flag</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLSAION</name>
+              <description>PLLSAI enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
             <field>
               <name>PLLI2SRDY</name>
               <description>PLLI2S clock ready flag</description>
@@ -11123,13 +11137,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI5ENR</name>
+              <name>SPI5EN</name>
               <description>SPI5 clock enable</description>
               <bitOffset>20</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI6ENR</name>
+              <name>SPI6EN</name>
               <description>SPI6 clock enable</description>
               <bitOffset>21</bitOffset>
               <bitWidth>1</bitWidth>
diff --git a/stm32f4/STM32F437.svd b/stm32f4/STM32F437.svd
index f607f57..097bfe6 100644
--- a/stm32f4/STM32F437.svd
+++ b/stm32f4/STM32F437.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F437</name>
-  <version>1.2</version>
+  <version>1.3</version>
   <description>STM32F437</description>
   <cpu>
     <name>CM4</name>
@@ -7907,6 +7907,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
           <size>0x20</size>
           <resetValue>0x00000083</resetValue>
           <fields>
+            <field>
+              <name>PLLSAIRDY</name>
+              <description>PLLSAI clock ready flag</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLSAION</name>
+              <description>PLLSAI enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
             <field>
               <name>PLLI2SRDY</name>
               <description>PLLI2S clock ready flag</description>
@@ -9285,13 +9299,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI5ENR</name>
+              <name>SPI5EN</name>
               <description>SPI5 clock enable</description>
               <bitOffset>20</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI6ENR</name>
+              <name>SPI6EN</name>
               <description>SPI6 clock enable</description>
               <bitOffset>21</bitOffset>
               <bitWidth>1</bitWidth>
diff --git a/stm32f4/STM32F439.svd b/stm32f4/STM32F439.svd
index 0cd94ba..ca2c3a9 100644
--- a/stm32f4/STM32F439.svd
+++ b/stm32f4/STM32F439.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F439</name>
-  <version>1.2</version>
+  <version>1.3</version>
   <description>STM32F439</description>
   <cpu>
     <name>CM4</name>
@@ -9727,6 +9727,20 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
           <size>0x20</size>
           <resetValue>0x00000083</resetValue>
           <fields>
+            <field>
+              <name>PLLSAIRDY</name>
+              <description>PLLSAI clock ready flag</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
+            <field>
+              <name>PLLSAION</name>
+              <description>PLLSAI enable</description>
+              <bitOffset>28</bitOffset>
+              <bitWidth>1</bitWidth>
+              <access>read-write</access>
+            </field>
             <field>
               <name>PLLI2SRDY</name>
               <description>PLLI2S clock ready flag</description>
@@ -11105,13 +11119,13 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI5ENR</name>
+              <name>SPI5EN</name>
               <description>SPI5 clock enable</description>
               <bitOffset>20</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>SPI6ENR</name>
+              <name>SPI6EN</name>
               <description>SPI6 clock enable</description>
               <bitOffset>21</bitOffset>
               <bitWidth>1</bitWidth>
diff --git a/stm32f4/STM32F446.svd b/stm32f4/STM32F446.svd
index f144c0e..d3b9fdd 100644
--- a/stm32f4/STM32F446.svd
+++ b/stm32f4/STM32F446.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F446</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32F446</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F469.svd b/stm32f4/STM32F469.svd
index aa650a9..de225a4 100644
--- a/stm32f4/STM32F469.svd
+++ b/stm32f4/STM32F469.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F469</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32F469</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32f4/STM32F479.svd b/stm32f4/STM32F479.svd
index bc119b6..4c4e885 100644
--- a/stm32f4/STM32F479.svd
+++ b/stm32f4/STM32F479.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32F479</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32F479</description>
   <cpu>
     <name>CM4</name>
diff --git a/stm32g0/STM32G030.svd b/stm32g0/STM32G030.svd
index 962f32c..02d7eef 100644
--- a/stm32g0/STM32G030.svd
+++ b/stm32g0/STM32G030.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G030</name>
-  <version>1.5</version>
+  <version>1.6</version>
   <description>STM32G030</description>
   <cpu>
     <name>CM0</name>
diff --git a/stm32g0/STM32G031.svd b/stm32g0/STM32G031.svd
index d19c5d0..c0e05c3 100644
--- a/stm32g0/STM32G031.svd
+++ b/stm32g0/STM32G031.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G031</name>
-  <version>1.5</version>
+  <version>1.6</version>
   <description>STM32G031</description>
     <cpu>
     <name>CM0</name>
@@ -454,7 +454,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -463,7 +463,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -517,6 +529,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G041.svd b/stm32g0/STM32G041.svd
index c54bd5a..be6830e 100644
--- a/stm32g0/STM32G041.svd
+++ b/stm32g0/STM32G041.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G041</name>
-  <version>1.4</version>
+  <version>1.5</version>
   <description>STM32G041</description>
   <cpu>
     <name>CM0</name>
@@ -454,7 +454,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -463,7 +463,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -517,6 +529,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G050.svd b/stm32g0/STM32G050.svd
index beb5d42..dd061d0 100644
--- a/stm32g0/STM32G050.svd
+++ b/stm32g0/STM32G050.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -18,7 +18,7 @@ Copyright (c) 2023 STMicroelectronics.
 -->
 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G050</name>
-  <version>1.2</version>
+  <version>1.3</version>
   <description>STM32G050</description>
   <cpu>
     <name>CM0</name>
diff --git a/stm32g0/STM32G051.svd b/stm32g0/STM32G051.svd
index a0e88aa..8a7a349 100644
--- a/stm32g0/STM32G051.svd
+++ b/stm32g0/STM32G051.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -18,7 +18,7 @@ Copyright (c) 2023 STMicroelectronics.
 -->
 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G051</name>
-  <version>1.3</version>
+  <version>1.4</version>
   <description>STM32G051</description>
   <cpu>
     <name>CM0</name>
@@ -12552,7 +12552,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -12561,7 +12561,19 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -12615,6 +12627,12 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G061.svd b/stm32g0/STM32G061.svd
index 52c84bf..ea2cf00 100644
--- a/stm32g0/STM32G061.svd
+++ b/stm32g0/STM32G061.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -18,7 +18,7 @@ Copyright (c) 2023 STMicroelectronics.
 -->
 <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G061</name>
-  <version>1.3</version>
+  <version>1.4</version>
   <description>STM32G061</description>
   <cpu>
     <name>CM0</name>
@@ -12618,7 +12618,7 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -12627,7 +12627,19 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -12681,6 +12693,12 @@ Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RG
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G070.svd b/stm32g0/STM32G070.svd
index 028a85c..fe32d1d 100644
--- a/stm32g0/STM32G070.svd
+++ b/stm32g0/STM32G070.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G070</name>
-  <version>1.8</version>
+  <version>1.9</version>
   <description>STM32G070</description>
   <cpu>
     <name>CM0</name>
diff --git a/stm32g0/STM32G071.svd b/stm32g0/STM32G071.svd
index 86b685d..88f4c24 100644
--- a/stm32g0/STM32G071.svd
+++ b/stm32g0/STM32G071.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G071</name>
-  <version>2.4</version>
+  <version>2.5</version>
   <description>STM32G071</description>
   <cpu>
     <name>CM0</name>
@@ -535,7 +535,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -544,7 +544,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -598,6 +610,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G081.svd b/stm32g0/STM32G081.svd
index a984408..46bdcd1 100644
--- a/stm32g0/STM32G081.svd
+++ b/stm32g0/STM32G081.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G081</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32G081</description>
   <cpu>
     <name>CM0</name>
@@ -535,7 +535,7 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -544,7 +544,19 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -598,6 +610,12 @@ xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G0B0.svd b/stm32g0/STM32G0B0.svd
index 98bc3a7..38a305f 100644
--- a/stm32g0/STM32G0B0.svd
+++ b/stm32g0/STM32G0B0.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G0B0</name>
-  <version>1.5</version>
+  <version>1.6</version>
   <description>STM32G0B0</description>
   <cpu>
     <name>CM0</name>
diff --git a/stm32g0/STM32G0B1.svd b/stm32g0/STM32G0B1.svd
index 98b05b5..95b102e 100644
--- a/stm32g0/STM32G0B1.svd
+++ b/stm32g0/STM32G0B1.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G0B1</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32G0B1</description>
   <cpu>
     <name>CM0</name>
@@ -15957,7 +15957,7 @@ These are protected write (P) bits, which means that write access by the bits is
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -15966,7 +15966,19 @@ These are protected write (P) bits, which means that write access by the bits is
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
+            </field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
             </field>
             <field>
               <name>STRT</name>
@@ -16020,6 +16032,12 @@ These are protected write (P) bits, which means that write access by the bits is
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>
diff --git a/stm32g0/STM32G0C1.svd b/stm32g0/STM32G0C1.svd
index cc3dd81..3dd664e 100644
--- a/stm32g0/STM32G0C1.svd
+++ b/stm32g0/STM32G0C1.svd
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8" standalone="no"?>
 <!--
-Copyright (c) 2023 STMicroelectronics.
+Copyright (c) 2024 STMicroelectronics.
 
  SPDX-License-Identifier: Apache-2.0
 
@@ -20,7 +20,7 @@ Copyright (c) 2023 STMicroelectronics.
 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
   <name>STM32G0C1</name>
-  <version>1.7</version>
+  <version>1.8</version>
   <description>STM32G0C1</description>
   <cpu>
     <name>CM0</name>
@@ -16858,7 +16858,7 @@ These are protected write (P) bits, which means that write access by the bits is
               <bitWidth>1</bitWidth>
             </field>
             <field>
-              <name>MER</name>
+              <name>MER1</name>
               <description>Mass erase</description>
               <bitOffset>2</bitOffset>
               <bitWidth>1</bitWidth>
@@ -16867,9 +16867,21 @@ These are protected write (P) bits, which means that write access by the bits is
               <name>PNB</name>
               <description>Page number</description>
               <bitOffset>3</bitOffset>
-              <bitWidth>6</bitWidth>
+              <bitWidth>10</bitWidth>
             </field>
             <field>
+            <field>
+              <name>BKER</name>
+              <description>Bank selection for erase operation</description>
+              <bitOffset>13</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
+            <field>
+              <name>MER2</name>
+              <description>Mass erase, Bank 2</description>
+              <bitOffset>15</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
               <name>STRT</name>
               <description>Start</description>
               <bitOffset>16</bitOffset>
@@ -16921,6 +16933,12 @@ These are protected write (P) bits, which means that write access by the bits is
               <bitOffset>28</bitOffset>
               <bitWidth>1</bitWidth>
             </field>
+            <field>
+              <name>SEC_PROT2</name>
+              <description>Securable memory area protection enable, Bank 2</description>
+              <bitOffset>29</bitOffset>
+              <bitWidth>1</bitWidth>
+            </field>
             <field>
               <name>OPTLOCK</name>
               <description>Options Lock</description>