Update pico-sdk to v1.3.1

Author: modm update bot

include/hardware/regs/dma.h

@@ -1,5 +1,5 @@
 /**
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -183,7 +183,6 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (0).
 #define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
@@ -457,7 +456,7 @@
 // Description : DMA Channel 1 Control and Status
 #define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)
 #define DMA_CH1_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH1_CTRL_TRIG_RESET  _u(0x00000800)
+#define DMA_CH1_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH1_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -572,8 +571,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (1).
-#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET  _u(0x1)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -846,7 +844,7 @@
 // Description : DMA Channel 2 Control and Status
 #define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)
 #define DMA_CH2_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH2_CTRL_TRIG_RESET  _u(0x00001000)
+#define DMA_CH2_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH2_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -961,8 +959,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (2).
-#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET  _u(0x2)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -1235,7 +1232,7 @@
 // Description : DMA Channel 3 Control and Status
 #define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)
 #define DMA_CH3_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH3_CTRL_TRIG_RESET  _u(0x00001800)
+#define DMA_CH3_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH3_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -1350,8 +1347,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (3).
-#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET  _u(0x3)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -1624,7 +1620,7 @@
 // Description : DMA Channel 4 Control and Status
 #define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)
 #define DMA_CH4_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH4_CTRL_TRIG_RESET  _u(0x00002000)
+#define DMA_CH4_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH4_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -1739,8 +1735,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (4).
-#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET  _u(0x4)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -2013,7 +2008,7 @@
 // Description : DMA Channel 5 Control and Status
 #define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)
 #define DMA_CH5_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH5_CTRL_TRIG_RESET  _u(0x00002800)
+#define DMA_CH5_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH5_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -2128,8 +2123,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (5).
-#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET  _u(0x5)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -2402,7 +2396,7 @@
 // Description : DMA Channel 6 Control and Status
 #define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)
 #define DMA_CH6_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH6_CTRL_TRIG_RESET  _u(0x00003000)
+#define DMA_CH6_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH6_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -2517,8 +2511,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (6).
-#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET  _u(0x6)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -2791,7 +2784,7 @@
 // Description : DMA Channel 7 Control and Status
 #define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)
 #define DMA_CH7_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH7_CTRL_TRIG_RESET  _u(0x00003800)
+#define DMA_CH7_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH7_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -2906,8 +2899,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (7).
-#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET  _u(0x7)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -3180,7 +3172,7 @@
 // Description : DMA Channel 8 Control and Status
 #define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)
 #define DMA_CH8_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH8_CTRL_TRIG_RESET  _u(0x00004000)
+#define DMA_CH8_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH8_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -3295,8 +3287,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (8).
-#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET  _u(0x8)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -3569,7 +3560,7 @@
 // Description : DMA Channel 9 Control and Status
 #define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)
 #define DMA_CH9_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH9_CTRL_TRIG_RESET  _u(0x00004800)
+#define DMA_CH9_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH9_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -3684,8 +3675,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (9).
-#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET  _u(0x9)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -3958,7 +3948,7 @@
 // Description : DMA Channel 10 Control and Status
 #define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)
 #define DMA_CH10_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH10_CTRL_TRIG_RESET  _u(0x00005000)
+#define DMA_CH10_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH10_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -4073,8 +4063,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (10).
-#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET  _u(0xa)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB    _u(11)
@@ -4347,7 +4336,7 @@
 // Description : DMA Channel 11 Control and Status
 #define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)
 #define DMA_CH11_CTRL_TRIG_BITS   _u(0xe1ffffff)
-#define DMA_CH11_CTRL_TRIG_RESET  _u(0x00005800)
+#define DMA_CH11_CTRL_TRIG_RESET  _u(0x00000000)
 // -----------------------------------------------------------------------------
 // Field       : DMA_CH11_CTRL_TRIG_AHB_ERROR
 // Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
@@ -4462,8 +4451,7 @@
 // Description : When this channel completes, it will trigger the channel
 //               indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
 //               channel)_.
-//               Reset value is equal to channel number (11).
-#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET  _u(0xb)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET  _u(0x0)
 #define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS   _u(0x00007800)
 #define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB    _u(14)
 #define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB    _u(11)

include/hardware/regs/sio.h

@@ -1,5 +1,5 @@
 /**
- * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -344,7 +344,7 @@
 //               q`.
 //               Any operand write starts a new calculation. The results appear
 //               in QUOTIENT, REMAINDER.
-//               UDIVIDEND/SDIVIDEND are aliases of the same internal register.
+//               UDIVISOR/SDIVISOR are aliases of the same internal register.
 //               The U alias starts an
 //               unsigned calculation, and the S alias starts a signed
 //               calculation.

include/hardware/structs/adc.h

@@ -86,6 +86,6 @@ typedef struct {
     io_ro_32 ints;
 } adc_hw_t;
 
-#define adc_hw ((adc_hw_t*)ADC_BASE)
+#define adc_hw ((adc_hw_t *)ADC_BASE)
 
 #endif

include/hardware/structs/bus_ctrl.h

@@ -72,6 +72,6 @@ typedef struct {
     bus_ctrl_perf_hw_t counter[4];
 } bus_ctrl_hw_t;
 
-#define bus_ctrl_hw ((bus_ctrl_hw_t*)BUSCTRL_BASE)
+#define bus_ctrl_hw ((bus_ctrl_hw_t *)BUSCTRL_BASE)
 
 #endif

include/hardware/structs/clocks.h

@@ -319,7 +319,7 @@ typedef struct {
     io_ro_32 ints;
 } clocks_hw_t;
 
-#define clocks_hw ((clocks_hw_t*)CLOCKS_BASE)
+#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
 
 static_assert( CLK_COUNT == 10, "");
 

include/hardware/structs/dma.h

@@ -194,8 +194,8 @@ typedef struct {
     } ch[NUM_DMA_CHANNELS];
 } dma_debug_hw_t;
 
-#define dma_hw ((dma_hw_t*)DMA_BASE)
-#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
+#define dma_hw ((dma_hw_t *)DMA_BASE)
+#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
 
 static_assert( NUM_DMA_TIMERS == 4, "");
 static_assert( NUM_DMA_CHANNELS == 12, "");

include/hardware/structs/i2c.h

@@ -327,7 +327,7 @@ typedef struct {
     io_ro_32 comp_type;
 } i2c_hw_t;
 
-#define i2c0_hw ((i2c_hw_t*)I2C0_BASE)
-#define i2c1_hw ((i2c_hw_t*)I2C1_BASE)
+#define i2c0_hw ((i2c_hw_t *)I2C0_BASE)
+#define i2c1_hw ((i2c_hw_t *)I2C1_BASE)
 
 #endif

include/hardware/structs/iobank0.h

@@ -208,7 +208,7 @@ typedef struct {
     io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
 } iobank0_hw_t;
 
-#define iobank0_hw ((iobank0_hw_t*)IO_BANK0_BASE)
+#define iobank0_hw ((iobank0_hw_t *)IO_BANK0_BASE)
 /// \end::iobank0_hw[]
 
 static_assert( NUM_BANK0_GPIOS == 30, "");

include/hardware/structs/ioqspi.h

@@ -167,7 +167,7 @@ typedef struct {
     io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
 } ioqspi_hw_t;
 
-#define ioqspi_hw ((ioqspi_hw_t*)IO_QSPI_BASE)
+#define ioqspi_hw ((ioqspi_hw_t *)IO_QSPI_BASE)
 
 static_assert( NUM_QSPI_GPIOS == 6, "");
 

include/hardware/structs/mpu.h

@@ -56,6 +56,6 @@ typedef struct {
     io_rw_32 rasr;
 } mpu_hw_t;
 
-#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
+#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
 
 #endif