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Commit 1c1fad1

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moatom
committed
Implement the CPU before debugging
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‎cpu.sml

Lines changed: 88 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -117,27 +117,27 @@ datatype instruction =
117117
| CMP of operand
118118
| CPX of operand
119119
| CPY of operand
120-
| DEC of address
120+
| DEC of operand
121121
| DEX of address
122122
| DEY of address
123123
| EOR of operand
124-
| INC of address
124+
| INC of operand
125125
| INX of address
126126
| INY of address
127127
| JMP of address
128128
| JSR of address
129129
| LDA of operand
130130
| LDX of operand
131131
| LDY of operand
132-
| LSR of address
132+
| LSR of operand
133133
| NOP of address
134134
| ORA of operand
135135
| PHA of address
136136
| PHP of address
137137
| PLA of address
138138
| PLP of address
139-
| ROL of address
140-
| ROR of address
139+
| ROL of operand
140+
| ROR of operand
141141
| RTI of address
142142
| RTS of address
143143
| SBC of operand
@@ -154,12 +154,35 @@ datatype instruction =
154154
| TXS of address
155155
| TYA of address
156156

157+
fun b2w bin = if bin then 0w1 else 0w0
158+
fun w2b word = if word = 0w0 then false else true
159+
fun p2Word p =
160+
(if #N p then 0w128 else 0w0)
161+
+ (if #V p then 0w64 else 0w0)
162+
+ (if #B5 p then 0w32 else 0w0)
163+
+ (if #B4 p then 0w16 else 0w0)
164+
+ (if #D p then 0w8 else 0w0)
165+
+ (if #I p then 0w4 else 0w0)
166+
+ (if #Z p then 0w2 else 0w0)
167+
+ (if #C p then 0w1 else 0w0)
168+
fun word2P w8 =
169+
{N = (Word8.andb (w8, 0wx80) = 0wx80),
170+
V = (Word8.andb (w8, 0wx40) = 0wx40),
171+
B5 = (Word8.andb (w8, 0wx20) = 0wx20),
172+
B4 = (Word8.andb (w8, 0wx10) = 0wx10),
173+
D = (Word8.andb (w8, 0wx04) = 0wx04),
174+
I = (Word8.andb (w8, 0wx03) = 0wx03),
175+
Z = (Word8.andb (w8, 0wx02) = 0wx02),
176+
C = (Word8.andb (w8, 0wx01) = 0wx01)}
177+
fun checkV (A, B, C): bool = not (w2b (Word8.>> ((Word8.xorb (A, B)), 0w7))) andalso w2b (Word8.>> ((Word8.xorb (A, C)), 0w7))
157178

179+
exception InvaildInstruction
158180
(* val exec : registers * instruction -> registers *)
159181
fun exec (regs, insn) =
160182
case insn of
161-
ADC x => let val v1 = value (regs, x) val v2 = v1 + #A regs in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0wx80) = 0wx80)}} end
183+
ADC x => let val v1 = value (regs, x) val v2 = v1 + #A regs + b2w (#C (#P regs)) in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), V = checkV (#A regs, v1, v2) ,Z = (v2=0w0), C = (v2 < #A regs)}} end
162184
| AND x => let val v1 = value (regs, x) val v2 = Word8.andb (#A regs, v1) in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0)}} end
185+
| ASL (Address Accumulator) => let val v1 = (#A regs) val v2 = v1 * 0w2 in regs # {A = v2 ,P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0wx80) = 0wx80)}} end
163186
| ASL (Address x) => let val v1 = value (regs, Address x) val v2 = v1 * 0w2 in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0wx80) = 0wx80)}}) end
164187
| BCC x => (if not (#C (#P regs)) then regs # {PC = address (regs, x)} else regs)
165188
| BCS x => (if #C (#P regs) then regs # {PC = address (regs, x)} else regs)
@@ -172,48 +195,52 @@ fun exec (regs, insn) =
172195
| BVC x => (if not (#V (#P regs)) then regs # {PC = address (regs, x)} else regs)
173196
| BVS x => (if #V (#P regs) then regs # {PC = address (regs, x)} else regs)
174197
| CLC x => (regs # {P = (#P regs) # {C=false}})
175-
| CLD x => regs
176-
| CLI x => regs
177-
| CLV x => regs
178-
| CMP x => regs
179-
| CPX x => regs
180-
| CPY x => regs
181-
| DEC x => regs
182-
| DEX x => regs
183-
| DEY x => regs
184-
| EOR x => regs
185-
| INC x => regs
186-
| INX x => regs
187-
| INY x => regs
198+
| CLD x => (regs # {P = (#P regs) # {D=false}})
199+
| CLI x => (regs # {P = (#P regs) # {I=false}})
200+
| CLV x => (regs # {P = (#P regs) # {V=false}})
201+
| CMP x => let val v1 = value (regs, x) val v2 = #A regs - v1 in regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = not (v2 > #A regs)}} end
202+
| CPX x => let val v1 = value (regs, x) val v2 = #X regs - v1 in regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = not (v2 > #X regs)}} end
203+
| CPY x => let val v1 = value (regs, x) val v2 = #Y regs - v1 in regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = not (v2 > #Y regs)}} end
204+
| DEC (Address x) => let val v1 = value (regs, Address x) val v2 = v1 - 0w1 in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0)}}) end
205+
| DEX x => let val v = #X regs - 0w1 in regs # {X = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
206+
| DEY x => let val v = #Y regs - 0w1 in regs # {Y = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
207+
| EOR x => let val v1 = value (regs, x) val v2 = Word8.xorb (#A regs, v1) in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0)}} end
208+
| INC (Address x) => let val v1 = value (regs, Address x) val v2 = v1 + 0w1 in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0)}}) end
209+
| INX x => let val v = #X regs + 0w1 in regs # {X = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
210+
| INY x => let val v = #Y regs + 0w1 in regs # {Y = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
188211
| JMP x => (regs # {PC = address (regs, x)})
189212
| JSR x => (write16 (0wx100+w8ToW16 (#S regs), #PC regs); regs # {S = (#S regs)-0w2, PC = address (regs, x)})
190213
| LDA x => let val v = value (regs, x) in regs # {A = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
191214
| LDX x => let val v = value (regs, x) in regs # {X = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
192-
| LDY x => regs
193-
| LSR x => regs
215+
| LDY x => let val v = value (regs, x) in regs # {Y = v, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
216+
| LSR (Address Accumulator) => let val v1 = (#A regs) val v2 = v1 div 0w2 in regs # {A = v2 ,P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0w1) = 0w1)}} end
217+
| LSR (Address x) => let val v1 = value (regs, Address x) val v2 = v1 div 0w2 in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0w1) = 0w1)}}) end
194218
| NOP x => regs
195-
| ORA x => regs
196-
| PHA x => regs
197-
| PHP x => regs
198-
| PLA x => regs
199-
| PLP x => regs
200-
| ROL x => regs
201-
| ROR x => regs
202-
| RTI x => regs
219+
| ORA x => let val v1 = value (regs, x) val v2 = Word8.orb (#A regs, v1) in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0)}} end
220+
| PHA x => (write (0wx100+w8ToW16 (#S regs), #A regs); regs # {S = (#S regs)-0w1})
221+
| PHP x => (write (0wx100+w8ToW16 (#S regs), p2Word (#P regs)); regs # {S = (#S regs)-0w1})
222+
| PLA x => let val v = read (0wx100 + w8ToW16 ((#S regs) + 0w1)) in regs # {A = v, S = (#S regs) + 0w1, P = (#P regs) # {N = (Word8.andb (v, 0wx80) = 0wx80), Z = (v=0w0)}} end
223+
| PLP x => let val v = Word8.orb (Word8.andb (read (0wx100 + w8ToW16 ((#S regs) + 0w1)), 0wxCF), Word8.andb (p2Word (#P regs), 0wx30)) in regs # {S = (#S regs) + 0w1, P = word2P v} end
224+
| ROL (Address Accumulator) => let val v1 = (#A regs) val v2 = v1 * 0w2 + b2w (#C (#P regs)) in regs # {A = v2 ,P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0wx80) = 0wx80)}} end
225+
| ROL (Address x) => let val v1 = value (regs, Address x) val v2 = v1 * 0w2 + b2w (#C (#P regs)) in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0wx80) = 0wx80)}}) end
226+
| ROR (Address Accumulator) => let val v1 = (#A regs) val v2 = v1 div 0w2 + 0w128 * b2w (#C (#P regs)) in regs # {A = v2 ,P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0w1) = 0w1)}} end
227+
| ROR (Address x) => let val v1 = value (regs, Address x) val v2 = v1 div 0w2 + 0w128 * b2w (#C (#P regs)) in (write (address (regs, x), v2); regs # {P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), Z = (v2=0w0), C = (Word8.andb (v1, 0w1) = 0w1)}}) end
228+
| RTI x => let val v1 = Word8.orb (Word8.andb (read (0wx100 + w8ToW16 ((#S regs) + 0w1)), 0wxCF), Word8.andb (p2Word (#P regs), 0wx30)) val v2 = read16 (0wx100 + w8ToW16 ((#S regs) + 0w2)) in regs # {PC = v2, S = (#S regs) + 0w3, P = word2P v1} end
203229
| RTS x => (regs # {PC = read16 (0wx100 + w8ToW16 ((#S regs) + 0w1)), S = (#S regs) + 0w2})
204-
| SBC x => regs
230+
| SBC x => let val v1 = 0w1 + Word8.notb (value (regs, x)) val v2 = v1 + #A regs - 0w1 + b2w (#C (#P regs)) in regs # {A = v2, P = (#P regs) # {N = (Word8.andb (v2, 0wx80) = 0wx80), V = checkV (#A regs, v1, v2) ,Z = (v2=0w0), C = (v2 < #A regs)}} end
205231
| SEC x => (regs # {P = (#P regs) # {C = true}})
206-
| SED x => regs
207-
| SEI x => regs
232+
| SED x => (regs # {P = (#P regs) # {D = true}})
233+
| SEI x => (regs # {P = (#P regs) # {I = true}})
208234
| STA x => (write (address (regs, x), #A regs); regs)
209235
| STX x => (write (address (regs, x), #X regs); regs)
210236
| STY x => (write (address (regs, x), #Y regs); regs)
211-
| TAX x => regs
212-
| TAY x => regs
213-
| TSX x => regs
214-
| TXA x => regs
215-
| TXS x => regs
216-
| TYA x => regs
237+
| TAX x => (regs # {X = #A regs, P = (#P regs) # {N = (Word8.andb (#A regs, 0wx80) = 0wx80), Z = (#A regs = 0w0)}})
238+
| TAY x => (regs # {Y = #A regs, P = (#P regs) # {N = (Word8.andb (#A regs, 0wx80) = 0wx80), Z = (#A regs = 0w0)}})
239+
| TSX x => (regs # {X = #S regs, P = (#P regs) # {N = (Word8.andb (#S regs, 0wx80) = 0wx80), Z = (#S regs = 0w0)}})
240+
| TXA x => (regs # {A = #X regs, P = (#P regs) # {N = (Word8.andb (#X regs, 0wx80) = 0wx80), Z = (#X regs = 0w0)}})
241+
| TXS x => (regs # {S = #X regs})
242+
| TYA x => (regs # {A = #Y regs, P = (#P regs) # {N = (Word8.andb (#Y regs, 0wx80) = 0wx80), Z = (#Y regs = 0w0)}})
243+
| _ => raise InvaildInstruction
217244

218245
exception FailedDecode
219246
fun fetchAndDecode (pc: word16): instruction * word16 =
@@ -252,57 +279,57 @@ fun fetchAndDecode (pc: word16): instruction * word16 =
252279
| 0wx21 => (AND (Address (IndexedIndirect (read (pc + 0w1)))), pc + 0w2)
253280
| 0wx24 => (BIT (Address (zp ())), pc + 0w2)
254281
| 0wx25 => (AND (Address (zp ())), pc + 0w2)
255-
| 0wx26 => (ROL (zp ()), pc + 0w2)
282+
| 0wx26 => (ROL (Address (zp ())), pc + 0w2)
256283
| 0wx28 => (PLP Implied, pc + 0w1)
257284
| 0wx29 => (AND (imm ()), pc + 0w2)
258-
| 0wx2A => (ROL Accumulator, pc + 0w1)
285+
| 0wx2A => (ROL (Address Accumulator), pc + 0w1)
259286
| 0wx2C => (BIT (Address (abs ())), pc + 0w3)
260287
| 0wx2D => (AND (Address (abs ())), pc + 0w3)
261-
| 0wx2E => (ROL (abs ()), pc + 0w3)
288+
| 0wx2E => (ROL (Address (abs ())), pc + 0w3)
262289
| 0wx30 => (BMI (rel ()), pc + 0w2)
263290
| 0wx31 => (AND (Address (izy ())), pc + 0w2)
264291
| 0wx35 => (AND (Address (zpx ())), pc + 0w2)
265-
| 0wx36 => (ROL (zpx ()), pc + 0w2)
292+
| 0wx36 => (ROL (Address (zpx ())), pc + 0w2)
266293
| 0wx38 => (SEC Implied, pc + 0w1)
267294
| 0wx39 => (AND (Address (aby ())), pc + 0w3)
268295
| 0wx3D => (AND (Address (abx ())), pc + 0w3)
269-
| 0wx3E => (ROL (abx ()), pc + 0w3)
296+
| 0wx3E => (ROL (Address (abx ())), pc + 0w3)
270297
| 0wx40 => (RTI Implied, pc + 0w1)
271298
| 0wx41 => (EOR (Address (izx ())), pc + 0w2)
272299
| 0wx45 => (EOR (Address (zp ())), pc + 0w2)
273-
| 0wx46 => (LSR (zp ()), pc + 0w2)
300+
| 0wx46 => (LSR (Address (zp ())), pc + 0w2)
274301
| 0wx48 => (PHA Implied, pc + 0w1)
275302
| 0wx49 => (EOR (imm ()), pc + 0w2)
276-
| 0wx4A => (LSR Accumulator, pc + 0w1)
303+
| 0wx4A => (LSR (Address Accumulator), pc + 0w1)
277304
| 0wx4C => (JMP (Absolute (read16 (pc + 0w1))), pc + 0w3)
278305
| 0wx4D => (EOR (Address (abs ())), pc + 0w3)
279-
| 0wx4E => (LSR (abs ()), pc + 0w3)
306+
| 0wx4E => (LSR (Address (abs ())), pc + 0w3)
280307
| 0wx50 => (BVC (rel ()), pc + 0w2)
281308
| 0wx51 => (EOR (Address (izy ())), pc + 0w2)
282309
| 0wx55 => (EOR (Address (zpx ())), pc + 0w2)
283-
| 0wx56 => (LSR (zpx ()), pc + 0w2)
310+
| 0wx56 => (LSR (Address (zpx ())), pc + 0w2)
284311
| 0wx58 => (CLI Implied, pc + 0w1)
285312
| 0wx59 => (EOR (Address (aby ())), pc + 0w3)
286313
| 0wx5D => (EOR (Address (abx ())), pc + 0w3)
287-
| 0wx5E => (LSR (abx ()), pc + 0w3)
314+
| 0wx5E => (LSR (Address (abx ())), pc + 0w3)
288315
| 0wx60 => (RTS Implied, pc + 0w1)
289316
| 0wx61 => (ADC (Address (izx ())), pc + 0w2)
290317
| 0wx65 => (ADC (Address (zp ())), pc + 0w2)
291-
| 0wx66 => (ROR (zp ()), pc + 0w2)
318+
| 0wx66 => (ROR (Address (zp ())), pc + 0w2)
292319
| 0wx68 => (PLA Implied, pc + 0w1)
293320
| 0wx69 => (ADC (imm ()), pc + 0w2)
294-
| 0wx6A => (ROR Accumulator, pc + 0w1)
321+
| 0wx6A => (ROR (Address Accumulator), pc + 0w1)
295322
| 0wx6C => (JMP (ind ()), pc + 0w3)
296323
| 0wx6D => (ADC (Address (abs ())), pc + 0w3)
297-
| 0wx6E => (ROR (abs ()), pc + 0w3)
324+
| 0wx6E => (ROR (Address (abs ())), pc + 0w3)
298325
| 0wx70 => (BVS (rel ()), pc + 0w2)
299326
| 0wx71 => (ADC (Address (izy ())), pc + 0w2)
300327
| 0wx75 => (ADC (Address (zpx ())), pc + 0w2)
301-
| 0wx76 => (ROR (zpx ()), pc + 0w2)
328+
| 0wx76 => (ROR (Address (zpx ())), pc + 0w2)
302329
| 0wx78 => (SEI Implied, pc + 0w1)
303330
| 0wx79 => (ADC (Address (aby ())), pc + 0w3)
304331
| 0wx7D => (ADC (Address (abx ())), pc + 0w3)
305-
| 0wx7E => (ROR (abx ()), pc + 0w3)
332+
| 0wx7E => (ROR (Address (abx ())), pc + 0w3)
306333
| 0wx81 => (STA (izx ()), pc + 0w2)
307334
| 0wx84 => (STY (zp ()), pc + 0w2)
308335
| 0wx85 => (STA (zp ()), pc + 0w2)
@@ -348,58 +375,43 @@ fun fetchAndDecode (pc: word16): instruction * word16 =
348375
| 0wxC1 => (CMP (Address (izx ())), pc + 0w2)
349376
| 0wxC4 => (CPY (Address (zp ())), pc + 0w2)
350377
| 0wxC5 => (CMP (Address (zp ())), pc + 0w2)
351-
| 0wxC6 => (DEC (zp ()), pc + 0w2)
378+
| 0wxC6 => (DEC (Address (zp ())), pc + 0w2)
352379
| 0wxC8 => (INY Implied, pc + 0w1)
353380
| 0wxC9 => (CMP (imm ()), pc + 0w2)
354381
| 0wxCA => (DEX Implied, pc + 0w1)
355382
| 0wxCC => (CPY (Address (abs ())), pc + 0w3)
356383
| 0wxCD => (CMP (Address (abs ())), pc + 0w3)
357-
| 0wxCE => (DEC (abs ()), pc + 0w3)
384+
| 0wxCE => (DEC (Address (abs ())), pc + 0w3)
358385
| 0wxD0 => (BNE (rel ()), pc + 0w2)
359386
| 0wxD1 => (CMP (Address (izy ())), pc + 0w2)
360387
| 0wxD5 => (CMP (Address (zpx ())), pc + 0w2)
361-
| 0wxD6 => (DEC (zpx ()), pc + 0w2)
388+
| 0wxD6 => (DEC (Address (zpx ())), pc + 0w2)
362389
| 0wxD8 => (CLD Implied, pc + 0w1)
363390
| 0wxD9 => (CMP (Address (aby ())), pc + 0w3)
364391
| 0wxDD => (CMP (Address (abx ())), pc + 0w3)
365-
| 0wxDE => (DEC (abx ()), pc + 0w3)
392+
| 0wxDE => (DEC (Address (abx ())), pc + 0w3)
366393
| 0wxE0 => (CPX (imm ()), pc + 0w2)
367394
| 0wxE1 => (SBC (Address (izx ())), pc + 0w2)
368395
| 0wxE4 => (CPX (Address (zp ())), pc + 0w2)
369396
| 0wxE5 => (SBC (Address (zp ())), pc + 0w2)
370-
| 0wxE6 => (INC (zp ()), pc + 0w2)
397+
| 0wxE6 => (INC (Address (zp ())), pc + 0w2)
371398
| 0wxE8 => (INX Implied, pc + 0w1)
372399
| 0wxE9 => (SBC (imm ()), pc + 0w2)
373400
| 0wxEA => (NOP Implied, pc + 0w1)
374401
| 0wxEC => (CPX (Address (abs ())), pc + 0w3)
375402
| 0wxED => (SBC (Address (abs ())), pc + 0w3)
376-
| 0wxEE => (INC (abs ()), pc + 0w3)
403+
| 0wxEE => (INC (Address (abs ())), pc + 0w3)
377404
| 0wxF0 => (BEQ (rel ()), pc + 0w2)
378405
| 0wxF1 => (SBC (Address (izy ())), pc + 0w2)
379406
| 0wxF5 => (SBC (Address (zpx ())), pc + 0w2)
380-
| 0wxF6 => (INC (zpx ()), pc + 0w2)
407+
| 0wxF6 => (INC (Address (zpx ())), pc + 0w2)
381408
| 0wxF8 => (SED Implied, pc + 0w1)
382409
| 0wxF9 => (SBC (Address (aby ())), pc + 0w3)
383410
| 0wxFD => (SBC (Address (abx ())), pc + 0w3)
384-
| 0wxFE => (INC (abx ()), pc + 0w3)
411+
| 0wxFE => (INC (Address (abx ())), pc + 0w3)
385412
| _ => raise FailedDecode
386413
end
387414

388-
fun p2Word p =
389-
let
390-
fun pow r 0 = 0w1
391-
| pow r n = r * pow r (n-1);
392-
in
393-
(if #N p then pow 0w2 7 else 0w0)
394-
+ (if #V p then pow 0w2 6 else 0w0)
395-
+ (if #B5 p then pow 0w2 5 else 0w0)
396-
+ (if #B4 p then pow 0w2 4 else 0w0)
397-
+ (if #D p then pow 0w2 3 else 0w0)
398-
+ (if #I p then pow 0w2 2 else 0w0)
399-
+ (if #Z p then pow 0w2 1 else 0w0)
400-
+ (if #C p then pow 0w2 0 else 0w0)
401-
end
402-
403415
fun prtRegs regs =
404416
print ( Word16.toString (#PC regs)
405417
^ "\tA:" ^ Word8.toString (#A regs)

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