Hard y Soft para Visera

Creación de archivos de Circuitos, PCB y Modelos 3D para el hardware, bloques y ejemplos para el software

Author: migrassi

3D Models/Caja_iCE40HX8K_Breakout_Board.stl

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+// Code generated by Icestudio 0.5.1n200403
+// Tue, 09 Jun 2020 20:51:29 GMT
+
+`default_nettype none
+
+module main (
+ input v403f0f,
+ input vef4d65,
+ input vf6b7c8,
+ input v4ec8f6,
+ input veb38c6,
+ input v25beec,
+ input vc959d3,
+ input vae9348,
+ output v3e0955,
+ output v6f653b,
+ output v371968,
+ output v7a319e,
+ output vde9f22,
+ output v3a9070,
+ output v0e5298,
+ output v22465b
+);
+ wire w0;
+ wire w1;
+ wire w2;
+ wire w3;
+ wire w4;
+ wire w5;
+ wire w6;
+ wire w7;
+ wire w8;
+ wire w9;
+ wire w10;
+ wire w11;
+ wire w12;
+ wire w13;
+ wire w14;
+ wire w15;
+ assign v3e0955 = w0;
+ assign w1 = v403f0f;
+ assign w2 = vef4d65;
+ assign v6f653b = w3;
+ assign v371968 = w4;
+ assign w5 = vf6b7c8;
+ assign v7a319e = w6;
+ assign w7 = v4ec8f6;
+ assign vde9f22 = w8;
+ assign w9 = veb38c6;
+ assign v3a9070 = w10;
+ assign w11 = v25beec;
+ assign v0e5298 = w12;
+ assign w13 = vc959d3;
+ assign v22465b = w14;
+ assign w15 = vae9348;
+ v8026ab v8620e7 (
+  .v758f58(w0),
+  .vedbc89(w1)
+ );
+ v8026ab vd3769a (
+  .vedbc89(w2),
+  .v758f58(w3)
+ );
+ v8026ab v078cd2 (
+  .v758f58(w4),
+  .vedbc89(w5)
+ );
+ v8026ab v74888f (
+  .v758f58(w6),
+  .vedbc89(w7)
+ );
+ v8026ab v751076 (
+  .v758f58(w8),
+  .vedbc89(w9)
+ );
+ v8026ab vc77573 (
+  .v758f58(w10),
+  .vedbc89(w11)
+ );
+ v8026ab va51dbd (
+  .v758f58(w12),
+  .vedbc89(w13)
+ );
+ v8026ab v878c57 (
+  .v758f58(w14),
+  .vedbc89(w15)
+ );
+endmodule
+
+module v8026ab (
+ input vedbc89,
+ output v758f58
+);
+ wire w0;
+ wire w1;
+ assign w0 = vedbc89;
+ assign v758f58 = w1;
+ v8026ab_v34955f v34955f (
+  .i(w0),
+  .o(w1)
+ );
+endmodule
+
+module v8026ab_v34955f (
+ input i,
+ output o
+);
+ // Pull up
+ 
+ wire din, dout, outen;
+ 
+ assign o = din;
+ 
+ SB_IO #(
+     .PIN_TYPE(6'b 1010_01),
+     .PULLUP(1'b 1)
+ ) io_pin (
+     .PACKAGE_PIN(i),
+     .OUTPUT_ENABLE(outen),
+     .D_OUT_0(dout),
+     .D_IN_0(din)
+ );
+endmodule