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Commits on Aug 18, 2021

• Added Vivado initialization code

  pConst

  committed
  261e056

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Commits on Aug 9, 2021

• Added exporting script for Vivado

  

  Konstantin Pavlov

  committed
  871c924

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Commits on Jul 29, 2021

• Updated version autoincrement script for Quartus

  

  Konstantin Pavlov

  committed
  0cb8ee9

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Commits on Jul 28, 2021

• Added SMA and tb

  pConst

  committed
  5156db4

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Commits on Jul 18, 2021

• Added universal block RAM fifo

  pConst

  committed
  4cd95ad

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Commits on Jul 9, 2021

• Added soft_latch module and testbench

  pConst

  committed
  1efbd7c

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Commits on Jul 7, 2021

• Update README.md

  pConst

  authored
  d262582

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Commits on Jul 6, 2021

• Updated lifo module to support FWFT and normal modes

  pConst

  committed
  2845a2a

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Commits on Jul 5, 2021

• Added single clock fifo modules (two variants)

  pConst

  committed
  452b357

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Commits on Jun 11, 2021

• Added synchronizer modules

  pConst

  committed
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Commits on Jun 3, 2021

• Added Vivado-specific scripts

  pConst

  committed
  d8beb37

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Commits on May 27, 2021

• Added Modelsim cleaning script

  pConst

  committed
  48e9dde

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Commits on Apr 12, 2021

• Updated Quartus Makefile and the reference project

  pConst

  committed
  aa52420

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Commits on Feb 5, 2021

• Test project for iterative compilation Quartus projects

  pConst

  committed
  111dbc6

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• Added fast counter sources

  pConst

  committed
  3619810

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• Added Quartus Makefile. Customizable and gives faster compilation

  pConst

  committed
  c243e1d

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Commits on Jan 27, 2021

• Added SV version of UART receiver

  pConst

  committed
  f3075c2

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Commits on Jan 26, 2021

• Rewriting UART modules to SystemVerilog

  pConst

  committed
  536a8b8

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• Minor code style update

  pConst

  committed
  b4b191c

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• Moved all bencmarks to the separate directory

  pConst

  committed
  cf3b4f5

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Commits on Dec 22, 2020

• Update README.md

  pConst

  authored
  1b84472

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Commits on Dec 18, 2020

• Added UART-like shifters for for simple synchronous messaging inside the FPGA or between FPGAs

  pConst

  committed
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Commits on Dec 17, 2020

• Updated benchmark projects. Added 'benchmark_results.txt' that i got on my machine

  pConst

  committed
  68922a3

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• Added benchmark project for Xilinx ISE Design Suite

  pConst

  committed
  d44ef08

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Commits on Dec 15, 2020

• Updates clean script for Quartus projects

  pConst

  committed
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Commits on Dec 11, 2020

• Added benchmark project for Gowin FPGAs

  pConst

  committed
  8980f48

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Commits on Nov 3, 2020

• Added cleaning script for Vivado projects

  pConst

  committed
  303665d

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• Fixes for delayed_event module

  pConst

  committed
  f5f3d32

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Commits on Oct 30, 2020

• Fixed usedw[] calculations in preview_fifo. Other minor fixes

  pConst

  committed
  2d2041a

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• Added project archieving for Quartus post-flow script

  pConst

  committed
  eb69a3a

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• Added dalayed_event module

  pConst

  committed
  002db31

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Commits on Aug 8, 2020

• Updated preview_fifo to support two word writes

  pConst

  committed
  3ddb800

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Commits on Jul 16, 2020

• Added ALTERA_TAPS delay type

  pConst

  committed
  aa1ac56

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Commits on Jul 9, 2020

• Updated delay module. Added block RAM implementation

  pConst

  committed
  b57c3a9

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• Added preview FIFO testbench

  pConst

  committed
  d2f436d

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