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atomic
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// atomic standard header
// Copyright (c) Microsoft Corporation.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
#pragma once
#ifndef _ATOMIC_
#define _ATOMIC_
#include <yvals.h>
#if _STL_COMPILER_PREPROCESSOR
#ifdef _M_CEE_PURE
#error <atomic> is not supported when compiling with /clr:pure.
#endif // _M_CEE_PURE
#include <cstddef>
#include <cstdint>
#include <cstring>
#include <xatomic.h>
#if _HAS_CXX20
#include <xatomic_wait.h>
#endif // _HAS_CXX20
#include <xthreads.h>
#pragma pack(push, _CRT_PACKING)
#pragma warning(push, _STL_WARNING_LEVEL)
#pragma warning(disable : _STL_DISABLED_WARNINGS)
_STL_DISABLE_CLANG_WARNINGS
#pragma push_macro("new")
#undef new
#ifdef _WIN64
#if _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1
#define _STD_COMPARE_EXCHANGE_128 _InterlockedCompareExchange128
#else // ^^^ _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 // _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 0 vvv
// 16-byte atomics are separately compiled for x64, as not all x64 hardware has the cmpxchg16b
// instruction; in the event this instruction is not available, the fallback is a global
// synchronization object shared by all 16-byte atomics.
// (Note: machines without this instruction typically have 2 cores or fewer, so this isn't too bad)
// All pointer parameters must be 16-byte aligned.
extern "C" _NODISCARD unsigned char __stdcall __std_atomic_compare_exchange_128(
_Inout_bytecount_(16) long long* _Destination, _In_ long long _ExchangeHigh, _In_ long long _ExchangeLow,
_Inout_bytecount_(16) long long* _ComparandResult) noexcept;
extern "C" _NODISCARD char __stdcall __std_atomic_has_cmpxchg16b() noexcept;
#define _STD_COMPARE_EXCHANGE_128 __std_atomic_compare_exchange_128
#endif // _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1
#endif // _WIN64
// Controls whether atomic::is_always_lock_free triggers for sizeof(void *) or 2 * sizeof(void *)
#if _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 || !defined(_M_X64) || defined(_M_ARM64EC)
#define _ATOMIC_HAS_DCAS 1
#else // ^^^ We always have DCAS / We only sometimes have DCAS vvv
#define _ATOMIC_HAS_DCAS 0
#endif // _STD_ATOMIC_ALWAYS_USE_CMPXCHG16B == 1 || !defined(_M_X64) || defined(_M_ARM64EC)
#define ATOMIC_BOOL_LOCK_FREE 2
#define ATOMIC_CHAR_LOCK_FREE 2
#ifdef __cpp_lib_char8_t
#define ATOMIC_CHAR8_T_LOCK_FREE 2
#endif // __cpp_lib_char8_t
#define ATOMIC_CHAR16_T_LOCK_FREE 2
#define ATOMIC_CHAR32_T_LOCK_FREE 2
#define ATOMIC_WCHAR_T_LOCK_FREE 2
#define ATOMIC_SHORT_LOCK_FREE 2
#define ATOMIC_INT_LOCK_FREE 2
#define ATOMIC_LONG_LOCK_FREE 2
#define ATOMIC_LLONG_LOCK_FREE 2
#define ATOMIC_POINTER_LOCK_FREE 2
// The following code is SHARED with vcruntime and any updates
// should be mirrored. Also: if any macros are added they should be
// #undefed in vcruntime as well
enum {
_Atomic_memory_order_relaxed,
_Atomic_memory_order_consume,
_Atomic_memory_order_acquire,
_Atomic_memory_order_release,
_Atomic_memory_order_acq_rel,
_Atomic_memory_order_seq_cst,
};
#ifndef _INVALID_MEMORY_ORDER
#ifdef _DEBUG
#define _INVALID_MEMORY_ORDER _STL_REPORT_ERROR("Invalid memory order")
#else // ^^^ _DEBUG / !_DEBUG vvv
#define _INVALID_MEMORY_ORDER
#endif // _DEBUG
#endif // _INVALID_MEMORY_ORDER
extern "C" inline void _Check_memory_order(const unsigned int _Order) noexcept {
if (_Order > _Atomic_memory_order_seq_cst) {
_INVALID_MEMORY_ORDER;
}
}
#define _Compiler_barrier() _STL_DISABLE_DEPRECATED_WARNING _ReadWriteBarrier() _STL_RESTORE_DEPRECATED_WARNING
#if defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
#define _Memory_barrier() __dmb(0xB) // inner shared data memory barrier
#define _Compiler_or_memory_barrier() _Memory_barrier()
#elif defined(_M_IX86) || defined(_M_X64)
// x86/x64 hardware only emits memory barriers inside _Interlocked intrinsics
#define _Compiler_or_memory_barrier() _Compiler_barrier()
#else // ^^^ x86/x64 / unsupported hardware vvv
#error Unsupported hardware
#endif // hardware
#if defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC))
#define _ATOMIC_CHOOSE_INTRINSIC(_Order, _Result, _Intrinsic, ...) \
_Check_memory_order(_Order); \
_Result = _Intrinsic(__VA_ARGS__)
#elif defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
#define _ATOMIC_CHOOSE_INTRINSIC(_Order, _Result, _Intrinsic, ...) \
switch (_Order) { \
case _Atomic_memory_order_relaxed: \
_Result = _INTRIN_RELAXED(_Intrinsic)(__VA_ARGS__); \
break; \
case _Atomic_memory_order_consume: \
case _Atomic_memory_order_acquire: \
_Result = _INTRIN_ACQUIRE(_Intrinsic)(__VA_ARGS__); \
break; \
case _Atomic_memory_order_release: \
_Result = _INTRIN_RELEASE(_Intrinsic)(__VA_ARGS__); \
break; \
default: \
_INVALID_MEMORY_ORDER; \
/* [[fallthrough]]; */ \
case _Atomic_memory_order_acq_rel: \
case _Atomic_memory_order_seq_cst: \
_Result = _Intrinsic(__VA_ARGS__); \
break; \
}
#endif // hardware
// note: these macros are _not_ always safe to use with a trailing semicolon,
// we avoid wrapping them in do {} while (0) because MSVC generates code for such loops
// in debug mode.
#define _ATOMIC_LOAD_VERIFY_MEMORY_ORDER(_Order_var) \
switch (_Order_var) { \
case _Atomic_memory_order_relaxed: \
break; \
case _Atomic_memory_order_consume: \
case _Atomic_memory_order_acquire: \
case _Atomic_memory_order_seq_cst: \
_Compiler_or_memory_barrier(); \
break; \
case _Atomic_memory_order_release: \
case _Atomic_memory_order_acq_rel: \
default: \
_INVALID_MEMORY_ORDER; \
break; \
}
#define _ATOMIC_STORE_PREFIX(_Width, _Ptr, _Desired) \
case _Atomic_memory_order_relaxed: \
__iso_volatile_store##_Width((_Ptr), (_Desired)); \
return; \
case _Atomic_memory_order_release: \
_Compiler_or_memory_barrier(); \
__iso_volatile_store##_Width((_Ptr), (_Desired)); \
return; \
default: \
case _Atomic_memory_order_consume: \
case _Atomic_memory_order_acquire: \
case _Atomic_memory_order_acq_rel: \
_INVALID_MEMORY_ORDER; \
/* [[fallthrough]]; */
#define _ATOMIC_STORE_SEQ_CST_ARM(_Width, _Ptr, _Desired) \
_Memory_barrier(); \
__iso_volatile_store##_Width((_Ptr), (_Desired)); \
_Memory_barrier();
#define _ATOMIC_STORE_SEQ_CST_X86_X64(_Width, _Ptr, _Desired) (void) _InterlockedExchange##_Width((_Ptr), (_Desired));
#define _ATOMIC_STORE_32_SEQ_CST_X86_X64(_Ptr, _Desired) \
(void) _InterlockedExchange(reinterpret_cast<volatile long*>(_Ptr), static_cast<long>(_Desired));
#define _ATOMIC_STORE_64_SEQ_CST_IX86(_Ptr, _Desired) \
_Compiler_barrier(); \
__iso_volatile_store64((_Ptr), (_Desired)); \
_Atomic_thread_fence(_Atomic_memory_order_seq_cst);
#if defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
#define _ATOMIC_STORE_SEQ_CST(_Width, _Ptr, _Desired) _ATOMIC_STORE_SEQ_CST_ARM(_Width, (_Ptr), (_Desired))
#define _ATOMIC_STORE_32_SEQ_CST(_Ptr, _Desired) _ATOMIC_STORE_SEQ_CST_ARM(32, (_Ptr), (_Desired))
#define _ATOMIC_STORE_64_SEQ_CST(_Ptr, _Desired) _ATOMIC_STORE_SEQ_CST_ARM(64, (_Ptr), (_Desired))
#else // ^^^ ARM32/ARM64/ARM64EC hardware / x86/x64 hardware vvv
#define _ATOMIC_STORE_SEQ_CST(_Width, _Ptr, _Desired) _ATOMIC_STORE_SEQ_CST_X86_X64(_Width, (_Ptr), (_Desired))
#define _ATOMIC_STORE_32_SEQ_CST(_Ptr, _Desired) _ATOMIC_STORE_32_SEQ_CST_X86_X64((_Ptr), (_Desired))
#ifdef _M_IX86
#define _ATOMIC_STORE_64_SEQ_CST(_Ptr, _Desired) _ATOMIC_STORE_64_SEQ_CST_IX86((_Ptr), (_Desired))
#else // ^^^ x86 / x64 vvv
#define _ATOMIC_STORE_64_SEQ_CST(_Ptr, _Desired) _ATOMIC_STORE_SEQ_CST_X86_X64(64, (_Ptr), (_Desired))
#endif // x86/x64
#endif // hardware
extern "C" inline void _Atomic_thread_fence(const unsigned int _Order) noexcept {
if (_Order == _Atomic_memory_order_relaxed) {
return;
}
#if defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC))
_Compiler_barrier();
if (_Order == _Atomic_memory_order_seq_cst) {
volatile long _Guard; // Not initialized to avoid an unnecessary operation; the value does not matter
// _mm_mfence could have been used, but it is not supported on older x86 CPUs and is slower on some recent CPUs.
// The memory fence provided by interlocked operations has some exceptions, but this is fine:
// std::atomic_thread_fence works with respect to other atomics only; it may not be a full fence for all ops.
#pragma warning(suppress : 6001) // "Using uninitialized memory '_Guard'"
#pragma warning(suppress : 28113) // "Accessing a local variable _Guard via an Interlocked function: This is an unusual
// usage which could be reconsidered."
(void) _InterlockedIncrement(&_Guard);
_Compiler_barrier();
}
#elif defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
_Memory_barrier();
#else // ^^^ ARM32/ARM64/ARM64EC / unsupported hardware vvv
#error Unsupported hardware
#endif // unsupported hardware
}
// End of code shared with vcruntime
_EXTERN_C
_Smtx_t* __stdcall __std_atomic_get_mutex(const void* _Key) noexcept;
_END_EXTERN_C
// Padding bits should not participate in cmpxchg comparison starting in C++20.
// Clang does not have __builtin_zero_non_value_bits to exclude these bits to implement this C++20 feature.
// The EDG front-end substitutes everything and runs into incomplete types passed to atomic<T>.
#if _HAS_CXX20 && !defined(__clang__) /* TRANSITION, LLVM-46685 */ && !defined(__EDG__)
#define _CMPXCHG_MASK_OUT_PADDING_BITS 1
#else
#define _CMPXCHG_MASK_OUT_PADDING_BITS 0
#endif
_STD_BEGIN
#if _CMPXCHG_MASK_OUT_PADDING_BITS
struct _Form_mask_t {};
_INLINE_VAR constexpr _Form_mask_t _Form_mask{};
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
template <class _Ty>
struct _Storage_for {
// uninitialized space to store a _Ty
alignas(_Ty) unsigned char _Storage[sizeof(_Ty)];
_Storage_for() = default;
_Storage_for(const _Storage_for&) = delete;
_Storage_for& operator=(const _Storage_for&) = delete;
#if _CMPXCHG_MASK_OUT_PADDING_BITS
explicit _Storage_for(_Form_mask_t) noexcept {
_CSTD memset(_Storage, 0xff, sizeof(_Ty));
__builtin_zero_non_value_bits(_Ptr());
}
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
_NODISCARD _Ty& _Ref() noexcept {
return reinterpret_cast<_Ty&>(_Storage);
}
_NODISCARD _Ty* _Ptr() noexcept {
return reinterpret_cast<_Ty*>(&_Storage);
}
};
#if _CMPXCHG_MASK_OUT_PADDING_BITS
template <class _Ty>
inline constexpr bool _Might_have_non_value_bits =
!has_unique_object_representations_v<_Ty> && !is_floating_point_v<_Ty>;
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
extern "C" inline void atomic_thread_fence(const memory_order _Order) noexcept {
::_Atomic_thread_fence(static_cast<unsigned int>(_Order));
}
extern "C" inline void atomic_signal_fence(const memory_order _Order) noexcept {
if (_Order != memory_order_relaxed) {
_Compiler_barrier();
}
}
template <class _Ty>
_Ty kill_dependency(_Ty _Arg) noexcept { // "magic" template that kills dependency ordering when called
return _Arg;
}
inline void _Check_store_memory_order(const memory_order _Order) noexcept {
switch (_Order) {
case memory_order_relaxed:
case memory_order_release:
case memory_order_seq_cst:
// nothing to do
break;
case memory_order_consume:
case memory_order_acquire:
case memory_order_acq_rel:
default:
_INVALID_MEMORY_ORDER;
break;
}
}
inline void _Check_load_memory_order(const memory_order _Order) noexcept {
switch (_Order) {
case memory_order_relaxed:
case memory_order_consume:
case memory_order_acquire:
case memory_order_seq_cst:
// nothing to do
break;
case memory_order_release:
case memory_order_acq_rel:
default:
_INVALID_MEMORY_ORDER;
break;
}
}
_NODISCARD inline memory_order _Combine_cas_memory_orders(
const memory_order _Success, const memory_order _Failure) noexcept {
// Finds upper bound of a compare/exchange memory order
// pair, according to the following partial order:
// seq_cst
// |
// acq_rel
// / \
// acquire release
// | |
// consume |
// \ /
// relaxed
static constexpr memory_order _Combined_memory_orders[6][6] = {// combined upper bounds
{memory_order_relaxed, memory_order_consume, memory_order_acquire, memory_order_release, memory_order_acq_rel,
memory_order_seq_cst},
{memory_order_consume, memory_order_consume, memory_order_acquire, memory_order_acq_rel, memory_order_acq_rel,
memory_order_seq_cst},
{memory_order_acquire, memory_order_acquire, memory_order_acquire, memory_order_acq_rel, memory_order_acq_rel,
memory_order_seq_cst},
{memory_order_release, memory_order_acq_rel, memory_order_acq_rel, memory_order_release, memory_order_acq_rel,
memory_order_seq_cst},
{memory_order_acq_rel, memory_order_acq_rel, memory_order_acq_rel, memory_order_acq_rel, memory_order_acq_rel,
memory_order_seq_cst},
{memory_order_seq_cst, memory_order_seq_cst, memory_order_seq_cst, memory_order_seq_cst, memory_order_seq_cst,
memory_order_seq_cst}};
_Check_memory_order(static_cast<unsigned int>(_Success));
_Check_load_memory_order(_Failure);
return _Combined_memory_orders[static_cast<int>(_Success)][static_cast<int>(_Failure)];
}
template <class _Integral, class _Ty>
_NODISCARD _Integral _Atomic_reinterpret_as(const _Ty& _Source) noexcept {
// interprets _Source as the supplied integral type
static_assert(is_integral_v<_Integral>, "Tried to reinterpret memory as non-integral");
if constexpr (is_integral_v<_Ty> && sizeof(_Integral) == sizeof(_Ty)) {
return static_cast<_Integral>(_Source);
} else if constexpr (is_pointer_v<_Ty> && sizeof(_Integral) == sizeof(_Ty)) {
return reinterpret_cast<_Integral>(_Source);
} else {
_Integral _Result{}; // zero padding bits
_CSTD memcpy(&_Result, _STD addressof(_Source), sizeof(_Source));
return _Result;
}
}
#if 1 // TRANSITION, ABI
template <class _Ty>
struct _Atomic_padded {
alignas(sizeof(_Ty)) mutable _Ty _Value; // align to sizeof(T); x86 stack aligns 8-byte objects on 4-byte boundaries
};
#else // ^^^ don't break ABI / break ABI vvv
template <class _Ty>
struct _Atomic_storage_traits { // properties for how _Ty is stored in an atomic
static constexpr size_t _Storage_size = sizeof(_Ty) == 1 ? 1
: sizeof(_Ty) == 2 ? 2
: sizeof(_Ty) <= 4 ? 4
: sizeof(_Ty) <= 8 ? 8
#if defined(_M_X64) || defined(_M_ARM64) || defined(_M_ARM64EC)
: sizeof(_Ty) <= 16 ? 16
#endif // 64 bits
: sizeof(_Ty);
static constexpr size_t _Padding_size = _Storage_size - sizeof(_Ty);
static constexpr bool _Uses_padding = _Padding_size != 0;
};
template <class _Ty>
struct _Atomic_storage_traits<_Ty&> { // properties for how _Ty is stored in an atomic_ref
static constexpr size_t _Storage_size = sizeof(_Ty);
static constexpr bool _Uses_padding = false;
};
template <class _Ty, bool = _Atomic_storage_traits<_Ty>::_Uses_padding>
struct _Atomic_padded { // aggregate to allow explicit constexpr zeroing of padding
alignas(_Atomic_storage_traits<_Ty>::_Storage_size) mutable _Ty _Value;
mutable unsigned char _Padding[_Atomic_storage_traits<_Ty>::_Padding_size];
};
template <class _Ty>
struct _Atomic_padded<_Ty, false> {
alignas(sizeof(_Ty)) mutable _Ty _Value; // align to sizeof(T); x86 stack aligns 8-byte objects on 4-byte boundaries
};
template <class _Ty>
struct _Atomic_padded<_Ty&, false> {
_Ty& _Value;
};
#endif // TRANSITION, ABI
template <class _Ty>
struct _Atomic_storage_types {
using _TStorage = _Atomic_padded<_Ty>;
using _Spinlock = long;
};
template <class _Ty>
struct _Atomic_storage_types<_Ty&> {
using _TStorage = _Ty&;
using _Spinlock = _Smtx_t*; // POINTER TO mutex
};
#if 1 // TRANSITION, ABI
template <class _Ty, size_t = sizeof(remove_reference_t<_Ty>)>
#else // ^^^ don't break ABI / break ABI vvv
template <class _Ty, size_t = _Atomic_storage_traits<_Ty>::_Storage_size>
#endif // TRANSITION, ABI
struct _Atomic_storage;
#if _HAS_CXX20
template <class _Ty, class _Value_type>
void _Atomic_wait_direct(
const _Atomic_storage<_Ty>* const _This, _Value_type _Expected_bytes, const memory_order _Order) noexcept {
const auto _Storage_ptr = _STD addressof(_This->_Storage);
for (;;) {
const _Value_type _Observed_bytes = _Atomic_reinterpret_as<_Value_type>(_This->load(_Order));
if (_Expected_bytes != _Observed_bytes) {
#if _CMPXCHG_MASK_OUT_PADDING_BITS
using _TVal = remove_reference_t<_Ty>;
if constexpr (_Might_have_non_value_bits<_TVal>) {
_Storage_for<_TVal> _Mask{_Form_mask};
const _Value_type _Mask_val = _Atomic_reinterpret_as<_Value_type>(_Mask._Ref());
if (((_Expected_bytes ^ _Observed_bytes) & _Mask_val) == 0) {
_Expected_bytes = _Observed_bytes;
continue;
}
}
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
return;
}
__std_atomic_wait_direct(_Storage_ptr, &_Expected_bytes, sizeof(_Value_type), _Atomic_wait_no_timeout);
}
}
#endif // _HAS_CXX20
#if 1 // TRANSITION, ABI, GH-1151
inline void _Atomic_lock_acquire(long& _Spinlock) noexcept {
#if defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC))
// Algorithm from Intel(R) 64 and IA-32 Architectures Optimization Reference Manual, May 2020
// Example 2-4. Contended Locks with Increasing Back-off Example - Improved Version, page 2-22
// The code in mentioned manual is covered by the 0BSD license.
int _Current_backoff = 1;
const int _Max_backoff = 64;
while (_InterlockedExchange(&_Spinlock, 1) != 0) {
while (__iso_volatile_load32(&reinterpret_cast<int&>(_Spinlock)) != 0) {
for (int _Count_down = _Current_backoff; _Count_down != 0; --_Count_down) {
_mm_pause();
}
_Current_backoff = _Current_backoff < _Max_backoff ? _Current_backoff << 1 : _Max_backoff;
}
}
#elif defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
while (_InterlockedExchange(&_Spinlock, 1) != 0) { // TRANSITION, GH-1133: _InterlockedExchange_acq
while (__iso_volatile_load32(&reinterpret_cast<int&>(_Spinlock)) != 0) {
__yield();
}
}
#else // ^^^ defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC) ^^^
#error Unsupported hardware
#endif
}
inline void _Atomic_lock_release(long& _Spinlock) noexcept {
#if defined(_M_IX86) || (defined(_M_X64) && !defined(_M_ARM64EC))
_InterlockedExchange(&_Spinlock, 0); // TRANSITION, GH-1133: same as ARM
#elif defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC)
_Memory_barrier();
__iso_volatile_store32(reinterpret_cast<int*>(&_Spinlock), 0);
_Memory_barrier(); // TRANSITION, GH-1133: remove
#else // ^^^ defined(_M_ARM) || defined(_M_ARM64) || defined(_M_ARM64EC) ^^^
#error Unsupported hardware
#endif
}
inline void _Atomic_lock_acquire(_Smtx_t* _Spinlock) noexcept {
_Smtx_lock_exclusive(_Spinlock);
}
inline void _Atomic_lock_release(_Smtx_t* _Spinlock) noexcept {
_Smtx_unlock_exclusive(_Spinlock);
}
template <class _Spinlock_t>
class _NODISCARD _Atomic_lock_guard {
public:
explicit _Atomic_lock_guard(_Spinlock_t& _Spinlock_) noexcept : _Spinlock(_Spinlock_) {
_Atomic_lock_acquire(_Spinlock);
}
~_Atomic_lock_guard() {
_Atomic_lock_release(_Spinlock);
}
_Atomic_lock_guard(const _Atomic_lock_guard&) = delete;
_Atomic_lock_guard& operator=(const _Atomic_lock_guard&) = delete;
private:
_Spinlock_t& _Spinlock;
};
#if _HAS_CXX20
template <class _Spinlock_t>
bool __stdcall _Atomic_wait_compare_non_lock_free(
const void* _Storage, void* _Comparand, size_t _Size, void* _Spinlock_raw) noexcept {
_Spinlock_t& _Spinlock = *static_cast<_Spinlock_t*>(_Spinlock_raw);
_Atomic_lock_acquire(_Spinlock);
const auto _Cmp_result = _CSTD memcmp(_Storage, _Comparand, _Size);
_Atomic_lock_release(_Spinlock);
return _Cmp_result == 0;
}
#ifdef _WIN64
inline bool __stdcall _Atomic_wait_compare_16_bytes(const void* _Storage, void* _Comparand, size_t, void*) noexcept {
const auto _Dest = static_cast<long long*>(const_cast<void*>(_Storage));
const auto _Cmp = static_cast<const long long*>(_Comparand);
alignas(16) long long _Tmp[2] = {_Cmp[0], _Cmp[1]};
#if defined(_M_X64) && !defined(_M_ARM64EC)
return _STD_COMPARE_EXCHANGE_128(_Dest, _Tmp[1], _Tmp[0], _Tmp) != 0;
#else // ^^^ _M_X64 / ARM64, _M_ARM64EC vvv
return _InterlockedCompareExchange128_nf(_Dest, _Tmp[1], _Tmp[0], _Tmp) != 0;
#endif // ^^^ ARM64, _M_ARM64EC ^^^
}
#endif // _WIN64
#endif // _HAS_CXX20
#endif // TRANSITION, ABI
template <class _Ty, size_t /* = ... */>
struct _Atomic_storage {
// Provides operations common to all specializations of std::atomic, load, store, exchange, and CAS.
// Locking version used when hardware has no atomic operations for sizeof(_Ty).
using _TVal = remove_reference_t<_Ty>;
using _Guard = _Atomic_lock_guard<typename _Atomic_storage_types<_Ty>::_Spinlock>;
_Atomic_storage() = default;
/* implicit */ constexpr _Atomic_storage(conditional_t<is_reference_v<_Ty>, _Ty, const _TVal> _Value) noexcept
: _Storage(_Value) {
// non-atomically initialize this atomic
}
void store(const _TVal _Value, const memory_order _Order = memory_order_seq_cst) noexcept {
// store with sequential consistency
_Check_store_memory_order(_Order);
_Guard _Lock{_Spinlock};
_Storage = _Value;
}
_NODISCARD _TVal load(const memory_order _Order = memory_order_seq_cst) const noexcept {
// load with sequential consistency
_Check_load_memory_order(_Order);
_Guard _Lock{_Spinlock};
_TVal _Local(_Storage);
return _Local;
}
_TVal exchange(const _TVal _Value, const memory_order _Order = memory_order_seq_cst) noexcept {
// exchange _Value with _Storage with sequential consistency
_Check_memory_order(static_cast<unsigned int>(_Order));
_Guard _Lock{_Spinlock};
_TVal _Result(_Storage);
_Storage = _Value;
return _Result;
}
bool compare_exchange_strong(_TVal& _Expected, const _TVal _Desired,
const memory_order _Order = memory_order_seq_cst) noexcept { // CAS with sequential consistency, plain
_Check_memory_order(static_cast<unsigned int>(_Order));
const auto _Storage_ptr = _STD addressof(_Storage);
const auto _Expected_ptr = _STD addressof(_Expected);
bool _Result;
#if _CMPXCHG_MASK_OUT_PADDING_BITS
__builtin_zero_non_value_bits(_Expected_ptr);
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
_Guard _Lock{_Spinlock};
#if _CMPXCHG_MASK_OUT_PADDING_BITS
if constexpr (_Might_have_non_value_bits<_TVal>) {
_Storage_for<_TVal> _Local;
const auto _Local_ptr = _Local._Ptr();
_CSTD memcpy(_Local_ptr, _Storage_ptr, sizeof(_TVal));
__builtin_zero_non_value_bits(_Local_ptr);
_Result = _CSTD memcmp(_Local_ptr, _Expected_ptr, sizeof(_TVal)) == 0;
} else {
_Result = _CSTD memcmp(_Storage_ptr, _Expected_ptr, sizeof(_TVal)) == 0;
}
#else // _CMPXCHG_MASK_OUT_PADDING_BITS
_Result = _CSTD memcmp(_Storage_ptr, _Expected_ptr, sizeof(_TVal)) == 0;
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
if (_Result) {
_CSTD memcpy(_Storage_ptr, _STD addressof(_Desired), sizeof(_TVal));
} else {
_CSTD memcpy(_Expected_ptr, _Storage_ptr, sizeof(_TVal));
}
return _Result;
}
#if _HAS_CXX20
void wait(_TVal _Expected, memory_order = memory_order_seq_cst) const noexcept {
const auto _Storage_ptr = _STD addressof(_Storage);
const auto _Expected_ptr = _STD addressof(_Expected);
for (;;) {
{
_Guard _Lock{_Spinlock};
if (_CSTD memcmp(_Storage_ptr, _Expected_ptr, sizeof(_TVal)) != 0) {
// contents differed, we might be done, check for padding
#if _CMPXCHG_MASK_OUT_PADDING_BITS
if constexpr (_Might_have_non_value_bits<_TVal>) {
_Storage_for<_TVal> _Local;
const auto _Local_ptr = _Local._Ptr();
_CSTD memcpy(_Local_ptr, _Storage_ptr, sizeof(_TVal));
__builtin_zero_non_value_bits(_Local_ptr);
__builtin_zero_non_value_bits(_Expected_ptr);
if (_CSTD memcmp(_Local_ptr, _Expected_ptr, sizeof(_TVal)) == 0) {
// _Storage differs from _Expected only by padding; copy the padding from _Storage into
// _Expected
_CSTD memcpy(_Expected_ptr, _Storage_ptr, sizeof(_TVal));
} else {
// truly different, we're done
return;
}
} else
#endif // #if _CMPXCHG_MASK_OUT_PADDING_BITS
{
return;
}
}
} // unlock
__std_atomic_wait_indirect(_Storage_ptr, _Expected_ptr, sizeof(_TVal), &_Spinlock,
&_Atomic_wait_compare_non_lock_free<decltype(_Spinlock)>, _Atomic_wait_no_timeout);
}
}
void notify_one() noexcept {
__std_atomic_notify_one_indirect(_STD addressof(_Storage));
}
void notify_all() noexcept {
__std_atomic_notify_all_indirect(_STD addressof(_Storage));
}
#endif // _HAS_CXX20
#if 1 // TRANSITION, ABI
protected:
void _Init_spinlock_for_ref() noexcept {
_Spinlock = __std_atomic_get_mutex(_STD addressof(_Storage));
}
private:
// Spinlock integer for non-lock-free atomic. <xthreads.h> mutex pointer for non-lock-free atomic_ref
mutable typename _Atomic_storage_types<_Ty>::_Spinlock _Spinlock{};
public:
_Ty _Storage{};
#else // ^^^ don't break ABI / break ABI vvv
_Ty _Storage;
mutable _Smtx_t _Mutex{};
#endif // TRANSITION, ABI
};
template <class _Ty>
struct _Atomic_storage<_Ty, 1> { // lock-free using 1-byte intrinsics
using _TVal = remove_reference_t<_Ty>;
_Atomic_storage() = default;
/* implicit */ constexpr _Atomic_storage(conditional_t<is_reference_v<_Ty>, _Ty, const _TVal> _Value) noexcept
: _Storage{_Value} {
// non-atomically initialize this atomic
}
void store(const _TVal _Value) noexcept { // store with sequential consistency
const auto _Mem = _Atomic_address_as<char>(_Storage);
const char _As_bytes = _Atomic_reinterpret_as<char>(_Value);
_ATOMIC_STORE_SEQ_CST(8, _Mem, _As_bytes)
}
void store(const _TVal _Value, const memory_order _Order) noexcept { // store with given memory order
const auto _Mem = _Atomic_address_as<char>(_Storage);
const char _As_bytes = _Atomic_reinterpret_as<char>(_Value);
switch (static_cast<unsigned int>(_Order)) {
_ATOMIC_STORE_PREFIX(8, _Mem, _As_bytes)
case _Atomic_memory_order_seq_cst:
store(_Value);
return;
}
}
_NODISCARD _TVal load() const noexcept { // load with sequential consistency
const auto _Mem = _Atomic_address_as<char>(_Storage);
char _As_bytes = __iso_volatile_load8(_Mem);
_Compiler_or_memory_barrier();
return reinterpret_cast<_TVal&>(_As_bytes);
}
_NODISCARD _TVal load(const memory_order _Order) const noexcept { // load with given memory order
const auto _Mem = _Atomic_address_as<char>(_Storage);
char _As_bytes = __iso_volatile_load8(_Mem);
_ATOMIC_LOAD_VERIFY_MEMORY_ORDER(static_cast<unsigned int>(_Order))
return reinterpret_cast<_TVal&>(_As_bytes);
}
_TVal exchange(const _TVal _Value, const memory_order _Order = memory_order_seq_cst) noexcept {
// exchange with given memory order
char _As_bytes;
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _As_bytes, _InterlockedExchange8,
_Atomic_address_as<char>(_Storage), _Atomic_reinterpret_as<char>(_Value));
return reinterpret_cast<_TVal&>(_As_bytes);
}
bool compare_exchange_strong(_TVal& _Expected, const _TVal _Desired,
const memory_order _Order = memory_order_seq_cst) noexcept { // CAS with given memory order
char _Expected_bytes = _Atomic_reinterpret_as<char>(_Expected); // read before atomic operation
char _Prev_bytes;
#if _CMPXCHG_MASK_OUT_PADDING_BITS
if constexpr (_Might_have_non_value_bits<_TVal>) {
_Storage_for<_TVal> _Mask{_Form_mask};
const char _Mask_val = _Atomic_reinterpret_as<char>(_Mask._Ref());
for (;;) {
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange8,
_Atomic_address_as<char>(_Storage), _Atomic_reinterpret_as<char>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
if ((_Prev_bytes ^ _Expected_bytes) & _Mask_val) {
reinterpret_cast<char&>(_Expected) = _Prev_bytes;
return false;
}
_Expected_bytes = (_Expected_bytes & _Mask_val) | (_Prev_bytes & ~_Mask_val);
}
}
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange8,
_Atomic_address_as<char>(_Storage), _Atomic_reinterpret_as<char>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
reinterpret_cast<char&>(_Expected) = _Prev_bytes;
return false;
}
#if _HAS_CXX20
void wait(const _TVal _Expected, const memory_order _Order = memory_order_seq_cst) const noexcept {
_Atomic_wait_direct(this, _Atomic_reinterpret_as<char>(_Expected), _Order);
}
void notify_one() noexcept {
__std_atomic_notify_one_direct(_STD addressof(_Storage));
}
void notify_all() noexcept {
__std_atomic_notify_all_direct(_STD addressof(_Storage));
}
#endif // _HAS_CXX20
typename _Atomic_storage_types<_Ty>::_TStorage _Storage;
};
template <class _Ty>
struct _Atomic_storage<_Ty, 2> { // lock-free using 2-byte intrinsics
using _TVal = remove_reference_t<_Ty>;
_Atomic_storage() = default;
/* implicit */ constexpr _Atomic_storage(conditional_t<is_reference_v<_Ty>, _Ty, const _TVal> _Value) noexcept
: _Storage{_Value} {
// non-atomically initialize this atomic
}
void store(const _TVal _Value) noexcept { // store with sequential consistency
const auto _Mem = _Atomic_address_as<short>(_Storage);
const short _As_bytes = _Atomic_reinterpret_as<short>(_Value);
_ATOMIC_STORE_SEQ_CST(16, _Mem, _As_bytes)
}
void store(const _TVal _Value, const memory_order _Order) noexcept { // store with given memory order
const auto _Mem = _Atomic_address_as<short>(_Storage);
const short _As_bytes = _Atomic_reinterpret_as<short>(_Value);
switch (static_cast<unsigned int>(_Order)) {
_ATOMIC_STORE_PREFIX(16, _Mem, _As_bytes)
case _Atomic_memory_order_seq_cst:
store(_Value);
return;
}
}
_NODISCARD _TVal load() const noexcept { // load with sequential consistency
const auto _Mem = _Atomic_address_as<short>(_Storage);
short _As_bytes = __iso_volatile_load16(_Mem);
_Compiler_or_memory_barrier();
return reinterpret_cast<_TVal&>(_As_bytes);
}
_NODISCARD _TVal load(const memory_order _Order) const noexcept { // load with given memory order
const auto _Mem = _Atomic_address_as<short>(_Storage);
short _As_bytes = __iso_volatile_load16(_Mem);
_ATOMIC_LOAD_VERIFY_MEMORY_ORDER(static_cast<unsigned int>(_Order))
return reinterpret_cast<_TVal&>(_As_bytes);
}
_TVal exchange(const _TVal _Value, const memory_order _Order = memory_order_seq_cst) noexcept {
// exchange with given memory order
short _As_bytes;
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _As_bytes, _InterlockedExchange16,
_Atomic_address_as<short>(_Storage), _Atomic_reinterpret_as<short>(_Value));
return reinterpret_cast<_TVal&>(_As_bytes);
}
bool compare_exchange_strong(_TVal& _Expected, const _TVal _Desired,
const memory_order _Order = memory_order_seq_cst) noexcept { // CAS with given memory order
short _Expected_bytes = _Atomic_reinterpret_as<short>(_Expected); // read before atomic operation
short _Prev_bytes;
#if _CMPXCHG_MASK_OUT_PADDING_BITS
if constexpr (_Might_have_non_value_bits<_Ty>) {
_Storage_for<_TVal> _Mask{_Form_mask};
const short _Mask_val = _Atomic_reinterpret_as<short>(_Mask._Ref());
for (;;) {
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange16,
_Atomic_address_as<short>(_Storage), _Atomic_reinterpret_as<short>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
if ((_Prev_bytes ^ _Expected_bytes) & _Mask_val) {
_CSTD memcpy(_STD addressof(_Expected), &_Prev_bytes, sizeof(_TVal));
return false;
}
_Expected_bytes = (_Expected_bytes & _Mask_val) | (_Prev_bytes & ~_Mask_val);
}
}
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange16,
_Atomic_address_as<short>(_Storage), _Atomic_reinterpret_as<short>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
_CSTD memcpy(_STD addressof(_Expected), &_Prev_bytes, sizeof(_Ty));
return false;
}
#if _HAS_CXX20
void wait(const _TVal _Expected, const memory_order _Order = memory_order_seq_cst) const noexcept {
_Atomic_wait_direct(this, _Atomic_reinterpret_as<short>(_Expected), _Order);
}
void notify_one() noexcept {
__std_atomic_notify_one_direct(_STD addressof(_Storage));
}
void notify_all() noexcept {
__std_atomic_notify_all_direct(_STD addressof(_Storage));
}
#endif // _HAS_CXX20
typename _Atomic_storage_types<_Ty>::_TStorage _Storage;
};
template <class _Ty>
struct _Atomic_storage<_Ty, 4> { // lock-free using 4-byte intrinsics
using _TVal = remove_reference_t<_Ty>;
_Atomic_storage() = default;
/* implicit */ constexpr _Atomic_storage(conditional_t<is_reference_v<_Ty>, _Ty, const _TVal> _Value) noexcept
: _Storage{_Value} {
// non-atomically initialize this atomic
}
void store(const _TVal _Value) noexcept { // store with sequential consistency
const auto _Mem = _Atomic_address_as<int>(_Storage);
const int _As_bytes = _Atomic_reinterpret_as<int>(_Value);
_ATOMIC_STORE_32_SEQ_CST(_Mem, _As_bytes)
}
void store(const _TVal _Value, const memory_order _Order) noexcept { // store with given memory order
const auto _Mem = _Atomic_address_as<int>(_Storage);
const int _As_bytes = _Atomic_reinterpret_as<int>(_Value);
switch (static_cast<unsigned int>(_Order)) {
_ATOMIC_STORE_PREFIX(32, _Mem, _As_bytes)
case _Atomic_memory_order_seq_cst:
store(_Value);
return;
}
}
_NODISCARD _TVal load() const noexcept { // load with sequential consistency
const auto _Mem = _Atomic_address_as<int>(_Storage);
int _As_bytes = __iso_volatile_load32(_Mem);
_Compiler_or_memory_barrier();
return reinterpret_cast<_TVal&>(_As_bytes);
}
_NODISCARD _TVal load(const memory_order _Order) const noexcept { // load with given memory order
const auto _Mem = _Atomic_address_as<int>(_Storage);
int _As_bytes = __iso_volatile_load32(_Mem);
_ATOMIC_LOAD_VERIFY_MEMORY_ORDER(static_cast<unsigned int>(_Order))
return reinterpret_cast<_TVal&>(_As_bytes);
}
_TVal exchange(const _TVal _Value, const memory_order _Order = memory_order_seq_cst) noexcept {
// exchange with given memory order
long _As_bytes;
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _As_bytes, _InterlockedExchange,
_Atomic_address_as<long>(_Storage), _Atomic_reinterpret_as<long>(_Value));
return reinterpret_cast<_TVal&>(_As_bytes);
}
bool compare_exchange_strong(_TVal& _Expected, const _TVal _Desired,
const memory_order _Order = memory_order_seq_cst) noexcept { // CAS with given memory order
long _Expected_bytes = _Atomic_reinterpret_as<long>(_Expected); // read before atomic operation
long _Prev_bytes;
#if _CMPXCHG_MASK_OUT_PADDING_BITS
if constexpr (_Might_have_non_value_bits<_TVal>) {
_Storage_for<_TVal> _Mask{_Form_mask};
const long _Mask_val = _Atomic_reinterpret_as<long>(_Mask);
for (;;) {
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange,
_Atomic_address_as<long>(_Storage), _Atomic_reinterpret_as<long>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
if ((_Prev_bytes ^ _Expected_bytes) & _Mask_val) {
_CSTD memcpy(_STD addressof(_Expected), &_Prev_bytes, sizeof(_TVal));
return false;
}
_Expected_bytes = (_Expected_bytes & _Mask_val) | (_Prev_bytes & ~_Mask_val);
}
}
#endif // _CMPXCHG_MASK_OUT_PADDING_BITS
_ATOMIC_CHOOSE_INTRINSIC(static_cast<unsigned int>(_Order), _Prev_bytes, _InterlockedCompareExchange,
_Atomic_address_as<long>(_Storage), _Atomic_reinterpret_as<long>(_Desired), _Expected_bytes);
if (_Prev_bytes == _Expected_bytes) {
return true;
}
_CSTD memcpy(_STD addressof(_Expected), &_Prev_bytes, sizeof(_TVal));
return false;
}
#if _HAS_CXX20
void wait(const _TVal _Expected, const memory_order _Order = memory_order_seq_cst) const noexcept {
_Atomic_wait_direct(this, _Atomic_reinterpret_as<long>(_Expected), _Order);
}
void notify_one() noexcept {
__std_atomic_notify_one_direct(_STD addressof(_Storage));
}
void notify_all() noexcept {
__std_atomic_notify_all_direct(_STD addressof(_Storage));
}
#endif // _HAS_CXX20
typename _Atomic_storage_types<_Ty>::_TStorage _Storage;
};
template <class _Ty>
struct _Atomic_storage<_Ty, 8> { // lock-free using 8-byte intrinsics
using _TVal = remove_reference_t<_Ty>;