From a2383c53a1537c152e0aed4880402edb16cc6577 Mon Sep 17 00:00:00 2001 From: Spinfast Date: Mon, 18 Dec 2023 23:14:41 -0600 Subject: [PATCH] Derive SAI blocks for 1176 from SAI1 All SAI instances can derive their register blocks from SAI1. While not every instance has multiple tx/rx lines and fifos the register layout can be reused for all SAI instances. The mcux sdk actually does this by casting the instance address to I2S_Type* which is a common struct with a common register layout. --- CHANGELOG.md | 5 + devices/imxrt1176_cm4.yaml | 3 + devices/imxrt1176_cm7.yaml | 6 + src/blocks/imxrt1176_cm4/sai.rs | 104 ++- src/blocks/imxrt1176_cm4/sai1.rs | 1311 ------------------------------ src/imxrt1176_cm4.rs | 49 +- src/imxrt1176_cm7.rs | 49 +- 7 files changed, 142 insertions(+), 1385 deletions(-) delete mode 100644 src/blocks/imxrt1176_cm4/sai1.rs diff --git a/CHANGELOG.md b/CHANGELOG.md index 4afd5c2a6a8d..1a269cc3798a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,11 @@ ## [Unreleased] +**BREAKING** In the 1176 API, there is only one SAI module. All SAI instances, +including those that only have a single channel, now appear to support multiple +channels. The user is responsible for making sure their SAI instance can +truly support multiple channels. + **BREAKING** The `flexio1` module is now called `flexio` for the 1010, 1015, and 1020 families. diff --git a/devices/imxrt1176_cm4.yaml b/devices/imxrt1176_cm4.yaml index a510c7c4f51a..a232c936b048 100644 --- a/devices/imxrt1176_cm4.yaml +++ b/devices/imxrt1176_cm4.yaml @@ -108,6 +108,9 @@ _derive: GPIO11: GPIO2 GPIO12: GPIO2 GPIO13: GPIO2 + SAI2: SAI1 + SAI3: SAI1 + SAI4: SAI1 # All of the directives below this comment are removing or simplifying # duplicated enumeratedValue fields in select register fields. These prevent diff --git a/devices/imxrt1176_cm7.yaml b/devices/imxrt1176_cm7.yaml index ab1d9658d169..da3e952cfb40 100644 --- a/devices/imxrt1176_cm7.yaml +++ b/devices/imxrt1176_cm7.yaml @@ -46,6 +46,12 @@ _add: size: 0x14 usage: registers +# SAI[2-4] should reuse the register block from SAI1 +_derive: + SAI2: SAI1 + SAI3: SAI1 + SAI4: SAI1 + # All of the directives below this comment are removing or simplifying # duplicated enumeratedValue fields in select register fields. These prevent # compilation due to duplicate symbols. diff --git a/src/blocks/imxrt1176_cm4/sai.rs b/src/blocks/imxrt1176_cm4/sai.rs index 43c370b41900..970f99647f54 100644 --- a/src/blocks/imxrt1176_cm4/sai.rs +++ b/src/blocks/imxrt1176_cm4/sai.rs @@ -18,11 +18,11 @@ pub struct RegisterBlock { #[doc = "Transmit Configuration 5"] pub TCR5: crate::RWRegister, #[doc = "Transmit Data"] - pub TDR0: crate::RWRegister, - _reserved0: [u8; 0x1c], + pub TDR: [crate::RWRegister; 4usize], + _reserved0: [u8; 0x10], #[doc = "Transmit FIFO"] - pub TFR0: crate::RORegister, - _reserved1: [u8; 0x1c], + pub TFR: [crate::RORegister; 4usize], + _reserved1: [u8; 0x10], #[doc = "Transmit Mask"] pub TMR: crate::RWRegister, _reserved2: [u8; 0x24], @@ -39,11 +39,11 @@ pub struct RegisterBlock { #[doc = "Receive Configuration 5"] pub RCR5: crate::RWRegister, #[doc = "Receive Data"] - pub RDR0: crate::RORegister, - _reserved3: [u8; 0x1c], + pub RDR: [crate::RORegister; 4usize], + _reserved3: [u8; 0x10], #[doc = "Receive FIFO"] - pub RFR0: crate::RORegister, - _reserved4: [u8; 0x1c], + pub RFR: [crate::RORegister; 4usize], + _reserved4: [u8; 0x10], #[doc = "Receive Mask"] pub RMR: crate::RWRegister, } @@ -471,7 +471,15 @@ pub mod TCR3 { #[doc = "Transmit Channel Enable"] pub mod TCE { pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; + pub const mask: u32 = 0x0f << offset; + pub mod R {} + pub mod W {} + pub mod RW {} + } + #[doc = "Channel FIFO Reset"] + pub mod CFR { + pub const offset: u32 = 24; + pub const mask: u32 = 0x0f << offset; pub mod R {} pub mod W {} pub mod RW {} @@ -588,6 +596,23 @@ pub mod TCR4 { pub const FPACK_3: u32 = 0x03; } } + #[doc = "FIFO Combine Mode"] + pub mod FCOMB { + pub const offset: u32 = 26; + pub const mask: u32 = 0x03 << offset; + pub mod R {} + pub mod W {} + pub mod RW { + #[doc = "FIFO combine mode disabled."] + pub const FCOMB_0: u32 = 0; + #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."] + pub const FCOMB_1: u32 = 0x01; + #[doc = "FIFO combine mode enabled on FIFO writes (by software)."] + pub const FCOMB_2: u32 = 0x02; + #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."] + pub const FCOMB_3: u32 = 0x03; + } + } #[doc = "FIFO Continue on Error"] pub mod FCONT { pub const offset: u32 = 28; @@ -630,7 +655,7 @@ pub mod TCR5 { } } #[doc = "Transmit Data"] -pub mod TDR0 { +pub mod TDR { #[doc = "Transmit Data Register"] pub mod TDR { pub const offset: u32 = 0; @@ -641,7 +666,7 @@ pub mod TDR0 { } } #[doc = "Transmit FIFO"] -pub mod TFR0 { +pub mod TFR { #[doc = "Read FIFO Pointer"] pub mod RFP { pub const offset: u32 = 0; @@ -658,6 +683,19 @@ pub mod TFR0 { pub mod W {} pub mod RW {} } + #[doc = "Write Channel Pointer"] + pub mod WCP { + pub const offset: u32 = 31; + pub const mask: u32 = 0x01 << offset; + pub mod R {} + pub mod W {} + pub mod RW { + #[doc = "No effect."] + pub const WCP_0: u32 = 0; + #[doc = "FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write."] + pub const WCP_1: u32 = 0x01; + } + } } #[doc = "Transmit Mask"] pub mod TMR { @@ -1042,7 +1080,15 @@ pub mod RCR3 { #[doc = "Receive Channel Enable"] pub mod RCE { pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; + pub const mask: u32 = 0x0f << offset; + pub mod R {} + pub mod W {} + pub mod RW {} + } + #[doc = "Channel FIFO Reset"] + pub mod CFR { + pub const offset: u32 = 24; + pub const mask: u32 = 0x0f << offset; pub mod R {} pub mod W {} pub mod RW {} @@ -1146,6 +1192,23 @@ pub mod RCR4 { pub const FPACK_3: u32 = 0x03; } } + #[doc = "FIFO Combine Mode"] + pub mod FCOMB { + pub const offset: u32 = 26; + pub const mask: u32 = 0x03 << offset; + pub mod R {} + pub mod W {} + pub mod RW { + #[doc = "FIFO combine mode disabled."] + pub const FCOMB_0: u32 = 0; + #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers)."] + pub const FCOMB_1: u32 = 0x01; + #[doc = "FIFO combine mode enabled on FIFO reads (by software)."] + pub const FCOMB_2: u32 = 0x02; + #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software)."] + pub const FCOMB_3: u32 = 0x03; + } + } #[doc = "FIFO Continue on Error"] pub mod FCONT { pub const offset: u32 = 28; @@ -1188,7 +1251,7 @@ pub mod RCR5 { } } #[doc = "Receive Data"] -pub mod RDR0 { +pub mod RDR { #[doc = "Receive Data Register"] pub mod RDR { pub const offset: u32 = 0; @@ -1199,7 +1262,7 @@ pub mod RDR0 { } } #[doc = "Receive FIFO"] -pub mod RFR0 { +pub mod RFR { #[doc = "Read FIFO Pointer"] pub mod RFP { pub const offset: u32 = 0; @@ -1208,6 +1271,19 @@ pub mod RFR0 { pub mod W {} pub mod RW {} } + #[doc = "Receive Channel Pointer"] + pub mod RCP { + pub const offset: u32 = 15; + pub const mask: u32 = 0x01 << offset; + pub mod R {} + pub mod W {} + pub mod RW { + #[doc = "No effect."] + pub const RCP_0: u32 = 0; + #[doc = "FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read."] + pub const RCP_1: u32 = 0x01; + } + } #[doc = "Write FIFO Pointer"] pub mod WFP { pub const offset: u32 = 16; diff --git a/src/blocks/imxrt1176_cm4/sai1.rs b/src/blocks/imxrt1176_cm4/sai1.rs deleted file mode 100644 index 0e83d2a6a55c..000000000000 --- a/src/blocks/imxrt1176_cm4/sai1.rs +++ /dev/null @@ -1,1311 +0,0 @@ -#[doc = "SAI"] -#[repr(C)] -pub struct RegisterBlock { - #[doc = "Version ID"] - pub VERID: crate::RORegister, - #[doc = "Parameter"] - pub PARAM: crate::RORegister, - #[doc = "Transmit Control"] - pub TCSR: crate::RWRegister, - #[doc = "Transmit Configuration 1"] - pub TCR1: crate::RWRegister, - #[doc = "Transmit Configuration 2"] - pub TCR2: crate::RWRegister, - #[doc = "Transmit Configuration 3"] - pub TCR3: crate::RWRegister, - #[doc = "Transmit Configuration 4"] - pub TCR4: crate::RWRegister, - #[doc = "Transmit Configuration 5"] - pub TCR5: crate::RWRegister, - #[doc = "Transmit Data"] - pub TDR: [crate::RWRegister; 4usize], - _reserved0: [u8; 0x10], - #[doc = "Transmit FIFO"] - pub TFR: [crate::RORegister; 4usize], - _reserved1: [u8; 0x10], - #[doc = "Transmit Mask"] - pub TMR: crate::RWRegister, - _reserved2: [u8; 0x24], - #[doc = "Receive Control"] - pub RCSR: crate::RWRegister, - #[doc = "Receive Configuration 1"] - pub RCR1: crate::RWRegister, - #[doc = "Receive Configuration 2"] - pub RCR2: crate::RWRegister, - #[doc = "Receive Configuration 3"] - pub RCR3: crate::RWRegister, - #[doc = "Receive Configuration 4"] - pub RCR4: crate::RWRegister, - #[doc = "Receive Configuration 5"] - pub RCR5: crate::RWRegister, - #[doc = "Receive Data"] - pub RDR: [crate::RORegister; 4usize], - _reserved3: [u8; 0x10], - #[doc = "Receive FIFO"] - pub RFR: [crate::RORegister; 4usize], - _reserved4: [u8; 0x10], - #[doc = "Receive Mask"] - pub RMR: crate::RWRegister, -} -#[doc = "Version ID"] -pub mod VERID { - #[doc = "Feature Specification Number"] - pub mod FEATURE { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Standard feature set."] - pub const STD: u32 = 0; - } - } - #[doc = "Minor Version Number"] - pub mod MINOR { - pub const offset: u32 = 16; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Major Version Number"] - pub mod MAJOR { - pub const offset: u32 = 24; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Parameter"] -pub mod PARAM { - #[doc = "Number of Datalines"] - pub mod DATALINE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "FIFO Size"] - pub mod FIFO { - pub const offset: u32 = 8; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Frame Size"] - pub mod FRAME { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Transmit Control"] -pub mod TCSR { - #[doc = "FIFO Request DMA Enable"] - pub mod FRDE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the DMA request."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the DMA request."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Warning DMA Enable"] - pub mod FWDE { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the DMA request."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the DMA request."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Request Interrupt Enable"] - pub mod FRIE { - pub const offset: u32 = 8; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Warning Interrupt Enable"] - pub mod FWIE { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Error Interrupt Enable"] - pub mod FEIE { - pub const offset: u32 = 10; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Sync Error Interrupt Enable"] - pub mod SEIE { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Word Start Interrupt Enable"] - pub mod WSIE { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Request Flag"] - pub mod FRF { - pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmit FIFO watermark has not been reached."] - pub const NO_FLAG: u32 = 0; - #[doc = "Transmit FIFO watermark has been reached."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "FIFO Warning Flag"] - pub mod FWF { - pub const offset: u32 = 17; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No enabled transmit FIFO is empty."] - pub const DISABLE: u32 = 0; - #[doc = "Enabled transmit FIFO is empty."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Error Flag"] - pub mod FEF { - pub const offset: u32 = 18; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmit underrun not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Transmit underrun detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Sync Error Flag"] - pub mod SEF { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Sync error not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Frame sync error detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Word Start Flag"] - pub mod WSF { - pub const offset: u32 = 20; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Start of word not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Start of word detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Software Reset"] - pub mod SR { - pub const offset: u32 = 24; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const DISABLE: u32 = 0; - #[doc = "Software reset."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Reset"] - pub mod FR { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const NO_EFFECT: u32 = 0; - #[doc = "FIFO reset."] - pub const RESET: u32 = 0x01; - } - } - #[doc = "Bit Clock Enable"] - pub mod BCE { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmit bit clock is disabled."] - pub const DISABLE: u32 = 0; - #[doc = "Transmit bit clock is enabled."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Debug Enable"] - pub mod DBGE { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmitter is disabled in Debug mode, after completing the current frame."] - pub const DISABLE: u32 = 0; - #[doc = "Transmitter is enabled in Debug mode."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Stop Enable"] - pub mod STOPE { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmitter disabled in Stop mode."] - pub const DISABLE: u32 = 0; - #[doc = "Transmitter enabled in Stop mode."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Transmitter Enable"] - pub mod TE { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Transmitter is disabled."] - pub const DISABLE: u32 = 0; - #[doc = "Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame."] - pub const ENABLE: u32 = 0x01; - } - } -} -#[doc = "Transmit Configuration 1"] -pub mod TCR1 { - #[doc = "Transmit FIFO Watermark"] - pub mod TFW { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Transmit Configuration 2"] -pub mod TCR2 { - #[doc = "Bit Clock Divide"] - pub mod DIV { - pub const offset: u32 = 0; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Bit Clock Bypass"] - pub mod BYP { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Internal bit clock is generated from bit clock divider."] - pub const DISABLE: u32 = 0; - #[doc = "Internal bit clock is divide by one of the audio master clock."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Bit Clock Direction"] - pub mod BCD { - pub const offset: u32 = 24; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bit clock is generated externally in Slave mode."] - pub const EXT_IN_SLAVE: u32 = 0; - #[doc = "Bit clock is generated internally in Master mode."] - pub const INT_IN_MASTER: u32 = 0x01; - } - } - #[doc = "Bit Clock Polarity"] - pub mod BCP { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge."] - pub const ACTIVE_HIGH: u32 = 0; - #[doc = "Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge."] - pub const ACTIVE_LOW: u32 = 0x01; - } - } - #[doc = "MCLK Select"] - pub mod MSEL { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bus Clock selected."] - pub const BUS_CLOCK: u32 = 0; - #[doc = "Master Clock (MCLK) 1 option selected."] - pub const MCLK1: u32 = 0x01; - #[doc = "Master Clock (MCLK) 2 option selected."] - pub const MCLK2: u32 = 0x02; - #[doc = "Master Clock (MCLK) 3 option selected."] - pub const MCLK3: u32 = 0x03; - } - } - #[doc = "Bit Clock Input"] - pub mod BCI { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const DISABLE: u32 = 0; - #[doc = "Internal logic is clocked as if bit clock was externally generated."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Bit Clock Swap"] - pub mod BCS { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Use the normal bit clock source."] - pub const DISABLE: u32 = 0; - #[doc = "Swap the bit clock source."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Synchronous Mode"] - pub mod SYNC { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Asynchronous mode."] - pub const ASYNC: u32 = 0; - #[doc = "Synchronous with receiver."] - pub const SYNC_W_RX: u32 = 0x01; - } - } -} -#[doc = "Transmit Configuration 3"] -pub mod TCR3 { - #[doc = "Word Flag Configuration"] - pub mod WDFL { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Transmit Channel Enable"] - pub mod TCE { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Channel FIFO Reset"] - pub mod CFR { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Transmit Configuration 4"] -pub mod TCR4 { - #[doc = "Frame Sync Direction"] - pub mod FSD { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame sync is generated externally in Slave mode."] - pub const EXT_IN_SLAVE_MODE: u32 = 0; - #[doc = "Frame sync is generated internally in Master mode."] - pub const INT_IN_MASTER_MODE: u32 = 0x01; - } - } - #[doc = "Frame Sync Polarity"] - pub mod FSP { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame sync is active high."] - pub const ACTIVE_HIGH: u32 = 0; - #[doc = "Frame sync is active low."] - pub const ACTIVE_LOW: u32 = 0x01; - } - } - #[doc = "On Demand Mode"] - pub mod ONDEM { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Internal frame sync is generated continuously."] - pub const CONTINUOUS_FRAME_SYNC: u32 = 0; - #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."] - pub const ON_DEMAND_FRAME_SYNC: u32 = 0x01; - } - } - #[doc = "Frame Sync Early"] - pub mod FSE { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame sync asserts with the first bit of the frame."] - pub const DISABLE: u32 = 0; - #[doc = "Frame sync asserts one bit before the first bit of the frame."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "MSB First"] - pub mod MF { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "LSB is transmitted first."] - pub const DISABLE: u32 = 0; - #[doc = "MSB is transmitted first."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Channel Mode"] - pub mod CHMOD { - pub const offset: u32 = 5; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled."] - pub const TDM_MODE: u32 = 0; - #[doc = "Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled."] - pub const OUTPUT_MODE: u32 = 0x01; - } - } - #[doc = "Sync Width"] - pub mod SYWD { - pub const offset: u32 = 8; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Frame size"] - pub mod FRSZ { - pub const offset: u32 = 16; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "FIFO Packing Mode"] - pub mod FPACK { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "FIFO packing is disabled."] - pub const DISABLED: u32 = 0; - #[doc = "8-bit FIFO packing is enabled."] - pub const EIGHT_BIT_FIFO_PACKING: u32 = 0x02; - #[doc = "16-bit FIFO packing is enabled."] - pub const SIXTEEN_BIT_FIFO_PACKING: u32 = 0x03; - } - } - #[doc = "FIFO Combine Mode"] - pub mod FCOMB { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "FIFO combine mode disabled."] - pub const DISABLED: u32 = 0; - #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers)."] - pub const ENABLED_ON_FIFO_READS: u32 = 0x01; - #[doc = "FIFO combine mode enabled on FIFO writes (by software)."] - pub const ENABLED_ON_FIFO_WRITES: u32 = 0x02; - #[doc = "FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software)."] - pub const ENABLED_ON_FIFO_READS_WRITES: u32 = 0x03; - } - } - #[doc = "FIFO Continue on Error"] - pub mod FCONT { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."] - pub const DISABLE: u32 = 0; - #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."] - pub const ENABLE: u32 = 0x01; - } - } -} -#[doc = "Transmit Configuration 5"] -pub mod TCR5 { - #[doc = "First Bit Shifted"] - pub mod FBT { - pub const offset: u32 = 8; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Word 0 Width"] - pub mod W0W { - pub const offset: u32 = 16; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Word N Width"] - pub mod WNW { - pub const offset: u32 = 24; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Transmit Data"] -pub mod TDR { - #[doc = "Transmit Data Register"] - pub mod TDR { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Transmit FIFO"] -pub mod TFR { - #[doc = "Read FIFO Pointer"] - pub mod RFP { - pub const offset: u32 = 0; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Write FIFO Pointer"] - pub mod WFP { - pub const offset: u32 = 16; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Write Channel Pointer"] - pub mod WCP { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const DISABLE: u32 = 0; - #[doc = "FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write."] - pub const ENABLE: u32 = 0x01; - } - } -} -#[doc = "Transmit Mask"] -pub mod TMR { - #[doc = "Transmit Word Mask"] - pub mod TWM { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Word N is enabled."] - pub const WORD_N_ENABLED: u32 = 0; - #[doc = "Word N is masked. The transmit data pins are tri-stated or drive zero when masked."] - pub const WORD_N_MASKED: u32 = 0x01; - } - } -} -#[doc = "Receive Control"] -pub mod RCSR { - #[doc = "FIFO Request DMA Enable"] - pub mod FRDE { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the DMA request."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the DMA request."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Warning DMA Enable"] - pub mod FWDE { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the DMA request."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the DMA request."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Request Interrupt Enable"] - pub mod FRIE { - pub const offset: u32 = 8; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Warning Interrupt Enable"] - pub mod FWIE { - pub const offset: u32 = 9; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Error Interrupt Enable"] - pub mod FEIE { - pub const offset: u32 = 10; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables the interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables the interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Sync Error Interrupt Enable"] - pub mod SEIE { - pub const offset: u32 = 11; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Word Start Interrupt Enable"] - pub mod WSIE { - pub const offset: u32 = 12; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Disables interrupt."] - pub const DISABLE: u32 = 0; - #[doc = "Enables interrupt."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "FIFO Request Flag"] - pub mod FRF { - pub const offset: u32 = 16; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receive FIFO watermark not reached."] - pub const BELOW_WATERMARK: u32 = 0; - #[doc = "Receive FIFO watermark has been reached."] - pub const WATERMARK_REACHED: u32 = 0x01; - } - } - #[doc = "FIFO Warning Flag"] - pub mod FWF { - pub const offset: u32 = 17; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No enabled receive FIFO is full."] - pub const NOT_FULL: u32 = 0; - #[doc = "Enabled receive FIFO is full."] - pub const FULL: u32 = 0x01; - } - } - #[doc = "FIFO Error Flag"] - pub mod FEF { - pub const offset: u32 = 18; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receive overflow not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Receive overflow detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Sync Error Flag"] - pub mod SEF { - pub const offset: u32 = 19; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Sync error not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Frame sync error detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Word Start Flag"] - pub mod WSF { - pub const offset: u32 = 20; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Start of word not detected."] - pub const NO_FLAG: u32 = 0; - #[doc = "Start of word detected."] - pub const FLAG: u32 = 0x01; - } - } - #[doc = "Software Reset"] - pub mod SR { - pub const offset: u32 = 24; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const NO_EFFECT: u32 = 0; - #[doc = "Software reset."] - pub const SW_RESET: u32 = 0x01; - } - } - #[doc = "FIFO Reset"] - pub mod FR { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const NO_EFFECT: u32 = 0; - #[doc = "FIFO reset."] - pub const FIFO_RESET: u32 = 0x01; - } - } - #[doc = "Bit Clock Enable"] - pub mod BCE { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receive bit clock is disabled."] - pub const DISABLE: u32 = 0; - #[doc = "Receive bit clock is enabled."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Debug Enable"] - pub mod DBGE { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receiver is disabled in Debug mode, after completing the current frame."] - pub const DISABLE: u32 = 0; - #[doc = "Receiver is enabled in Debug mode."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Stop Enable"] - pub mod STOPE { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receiver disabled in Stop mode."] - pub const DISABLE: u32 = 0; - #[doc = "Receiver enabled in Stop mode."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Receiver Enable"] - pub mod RE { - pub const offset: u32 = 31; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Receiver is disabled."] - pub const DISABLE: u32 = 0; - #[doc = "Receiver is enabled, or receiver has been disabled and has not yet reached end of frame."] - pub const ENABLE: u32 = 0x01; - } - } -} -#[doc = "Receive Configuration 1"] -pub mod RCR1 { - #[doc = "Receive FIFO Watermark"] - pub mod RFW { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Receive Configuration 2"] -pub mod RCR2 { - #[doc = "Bit Clock Divide"] - pub mod DIV { - pub const offset: u32 = 0; - pub const mask: u32 = 0xff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Bit Clock Bypass"] - pub mod BYP { - pub const offset: u32 = 23; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Internal bit clock is generated from bit clock divider."] - pub const DISABLE: u32 = 0; - #[doc = "Internal bit clock is divide by one of the audio master clock."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Bit Clock Direction"] - pub mod BCD { - pub const offset: u32 = 24; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bit clock is generated externally in Slave mode."] - pub const EXT_SLAVE_MODE: u32 = 0; - #[doc = "Bit clock is generated internally in Master mode."] - pub const INT_MASTER_MODE: u32 = 0x01; - } - } - #[doc = "Bit Clock Polarity"] - pub mod BCP { - pub const offset: u32 = 25; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge."] - pub const ACTIVE_HIGH: u32 = 0; - #[doc = "Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge."] - pub const ACTIVE_LOW: u32 = 0x01; - } - } - #[doc = "MCLK Select"] - pub mod MSEL { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Bus Clock selected."] - pub const BUS_CLOCK: u32 = 0; - #[doc = "Master Clock (MCLK) 1 option selected."] - pub const MCLK1: u32 = 0x01; - #[doc = "Master Clock (MCLK) 2 option selected."] - pub const MCLK2: u32 = 0x02; - #[doc = "Master Clock (MCLK) 3 option selected."] - pub const MCLK3: u32 = 0x03; - } - } - #[doc = "Bit Clock Input"] - pub mod BCI { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const NO_EFFECT: u32 = 0; - #[doc = "Internal logic is clocked as if bit clock was externally generated."] - pub const CLOCKED_AS_IF_EXT_GENERATED: u32 = 0x01; - } - } - #[doc = "Bit Clock Swap"] - pub mod BCS { - pub const offset: u32 = 29; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Use the normal bit clock source."] - pub const NORMAL: u32 = 0; - #[doc = "Swap the bit clock source."] - pub const SWAP_BIT_CLK_SOURCE: u32 = 0x01; - } - } - #[doc = "Synchronous Mode"] - pub mod SYNC { - pub const offset: u32 = 30; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Asynchronous mode."] - pub const ASYNC: u32 = 0; - #[doc = "Synchronous with transmitter."] - pub const SYNC_W_TX: u32 = 0x01; - } - } -} -#[doc = "Receive Configuration 3"] -pub mod RCR3 { - #[doc = "Word Flag Configuration"] - pub mod WDFL { - pub const offset: u32 = 0; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Receive Channel Enable"] - pub mod RCE { - pub const offset: u32 = 16; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Channel FIFO Reset"] - pub mod CFR { - pub const offset: u32 = 24; - pub const mask: u32 = 0x0f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Receive Configuration 4"] -pub mod RCR4 { - #[doc = "Frame Sync Direction"] - pub mod FSD { - pub const offset: u32 = 0; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame Sync is generated externally in Slave mode."] - pub const EXT_SLAVE_MODE: u32 = 0; - #[doc = "Frame Sync is generated internally in Master mode."] - pub const INT_MASTER_MODE: u32 = 0x01; - } - } - #[doc = "Frame Sync Polarity"] - pub mod FSP { - pub const offset: u32 = 1; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame sync is active high."] - pub const ACTIVE_HIGH: u32 = 0; - #[doc = "Frame sync is active low."] - pub const ACTIVE_LOW: u32 = 0x01; - } - } - #[doc = "On Demand Mode"] - pub mod ONDEM { - pub const offset: u32 = 2; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Internal frame sync is generated continuously."] - pub const DISABLE: u32 = 0; - #[doc = "Internal frame sync is generated when the FIFO warning flag is clear."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Frame Sync Early"] - pub mod FSE { - pub const offset: u32 = 3; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Frame sync asserts with the first bit of the frame."] - pub const DISABLE: u32 = 0; - #[doc = "Frame sync asserts one bit before the first bit of the frame."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "MSB First"] - pub mod MF { - pub const offset: u32 = 4; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "LSB is received first."] - pub const DISABLE: u32 = 0; - #[doc = "MSB is received first."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Sync Width"] - pub mod SYWD { - pub const offset: u32 = 8; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Frame Size"] - pub mod FRSZ { - pub const offset: u32 = 16; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "FIFO Packing Mode"] - pub mod FPACK { - pub const offset: u32 = 24; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "FIFO packing is disabled"] - pub const DISABLED: u32 = 0; - #[doc = "8-bit FIFO packing is enabled"] - pub const EIGHT_BIT_PACKING: u32 = 0x02; - #[doc = "16-bit FIFO packing is enabled"] - pub const SIXTEEN_BIT_PACKING: u32 = 0x03; - } - } - #[doc = "FIFO Combine Mode"] - pub mod FCOMB { - pub const offset: u32 = 26; - pub const mask: u32 = 0x03 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "FIFO combine mode disabled."] - pub const DISABLED: u32 = 0; - #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers)."] - pub const ENA_ON_FIFO_WRITES: u32 = 0x01; - #[doc = "FIFO combine mode enabled on FIFO reads (by software)."] - pub const ENA_ON_FIFO_READS: u32 = 0x02; - #[doc = "FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software)."] - pub const ENA_ON_FIFO_WRITES_READS: u32 = 0x03; - } - } - #[doc = "FIFO Continue on Error"] - pub mod FCONT { - pub const offset: u32 = 28; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared."] - pub const DISABLE: u32 = 0; - #[doc = "On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared."] - pub const ENABLE: u32 = 0x01; - } - } -} -#[doc = "Receive Configuration 5"] -pub mod RCR5 { - #[doc = "First Bit Shifted"] - pub mod FBT { - pub const offset: u32 = 8; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Word 0 Width"] - pub mod W0W { - pub const offset: u32 = 16; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Word N Width"] - pub mod WNW { - pub const offset: u32 = 24; - pub const mask: u32 = 0x1f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Receive Data"] -pub mod RDR { - #[doc = "Receive Data Register"] - pub mod RDR { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Receive FIFO"] -pub mod RFR { - #[doc = "Read FIFO Pointer"] - pub mod RFP { - pub const offset: u32 = 0; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } - #[doc = "Receive Channel Pointer"] - pub mod RCP { - pub const offset: u32 = 15; - pub const mask: u32 = 0x01 << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "No effect."] - pub const DISABLE: u32 = 0; - #[doc = "FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read."] - pub const ENABLE: u32 = 0x01; - } - } - #[doc = "Write FIFO Pointer"] - pub mod WFP { - pub const offset: u32 = 16; - pub const mask: u32 = 0x3f << offset; - pub mod R {} - pub mod W {} - pub mod RW {} - } -} -#[doc = "Receive Mask"] -pub mod RMR { - #[doc = "Receive Word Mask"] - pub mod RWM { - pub const offset: u32 = 0; - pub const mask: u32 = 0xffff_ffff << offset; - pub mod R {} - pub mod W {} - pub mod RW { - #[doc = "Word N is enabled."] - pub const WORD_N_ENABLED: u32 = 0; - #[doc = "Word N is masked."] - pub const WORD_N_MASKED: u32 = 0x01; - } - } -} diff --git a/src/imxrt1176_cm4.rs b/src/imxrt1176_cm4.rs index 46893d10b69a..0e6fb868fd4e 100644 --- a/src/imxrt1176_cm4.rs +++ b/src/imxrt1176_cm4.rs @@ -4562,6 +4562,8 @@ pub mod rtwdog { } #[path = "."] pub mod sai { + #[doc = "SAI"] + pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock; #[doc = "SAI"] pub const SAI2: *const RegisterBlock = 0x4040_8000 as *const RegisterBlock; #[doc = "SAI"] @@ -4572,6 +4574,20 @@ pub mod sai { mod blocks; pub use blocks::*; pub type Instance = crate::Instance; + pub type SAI1 = Instance<1>; + impl crate::private::Sealed for SAI1 {} + impl crate::Valid for SAI1 {} + impl SAI1 { + #[doc = r" Acquire a vaild, but possibly aliased, instance."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" See [the struct-level safety documentation](crate::Instance)."] + #[inline] + pub const unsafe fn instance() -> Self { + Instance::new(SAI1) + } + } pub type SAI2 = Instance<2>; impl crate::private::Sealed for SAI2 {} impl crate::Valid for SAI2 {} @@ -4616,40 +4632,13 @@ pub mod sai { } #[doc = r" Returns the instance number `N` for a peripheral instance."] pub fn number(rb: *const RegisterBlock) -> Option { - [(SAI2, 2), (SAI3, 3), (SAI4, 4)] + [(SAI1, 1), (SAI2, 2), (SAI3, 3), (SAI4, 4)] .into_iter() .find(|(ptr, _)| core::ptr::eq(rb, *ptr)) .map(|(_, inst)| inst) } } #[path = "."] -pub mod sai1 { - #[doc = "SAI"] - pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock; - #[path = "blocks/imxrt1176_cm4/sai1.rs"] - mod blocks; - pub use blocks::*; - pub type Instance = crate::Instance; - pub type SAI1 = Instance<{ crate::SOLE_INSTANCE }>; - impl crate::private::Sealed for SAI1 {} - impl crate::Valid for SAI1 {} - impl SAI1 { - #[doc = r" Acquire a vaild, but possibly aliased, instance."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" See [the struct-level safety documentation](crate::Instance)."] - #[inline] - pub const unsafe fn instance() -> Self { - Instance::new(SAI1) - } - } - #[doc = r" Returns the instance number `N` for a peripheral instance."] - pub fn number(rb: *const RegisterBlock) -> Option { - core::ptr::eq(rb, SAI1).then_some(0) - } -} -#[path = "."] pub mod sema4 { #[doc = "IPS_Semaphores"] pub const SEMA4: *const RegisterBlock = 0x40cc_8000 as *const RegisterBlock; @@ -5640,10 +5629,10 @@ pub struct Instances { pub RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2, pub RTWDOG3: rtwdog::RTWDOG3, pub RTWDOG4: rtwdog::RTWDOG4, + pub SAI1: sai::SAI1, pub SAI2: sai::SAI2, pub SAI3: sai::SAI3, pub SAI4: sai::SAI4, - pub SAI1: sai1::SAI1, pub SEMA4: sema4::SEMA4, pub SEMC: semc::SEMC, pub SNVS: snvs::SNVS, @@ -5845,10 +5834,10 @@ impl Instances { RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2::instance(), RTWDOG3: rtwdog::RTWDOG3::instance(), RTWDOG4: rtwdog::RTWDOG4::instance(), + SAI1: sai::SAI1::instance(), SAI2: sai::SAI2::instance(), SAI3: sai::SAI3::instance(), SAI4: sai::SAI4::instance(), - SAI1: sai1::SAI1::instance(), SEMA4: sema4::SEMA4::instance(), SEMC: semc::SEMC::instance(), SNVS: snvs::SNVS::instance(), diff --git a/src/imxrt1176_cm7.rs b/src/imxrt1176_cm7.rs index 3321eb58c02f..11889bb5bcff 100644 --- a/src/imxrt1176_cm7.rs +++ b/src/imxrt1176_cm7.rs @@ -4540,6 +4540,8 @@ pub mod rtwdog { } #[path = "."] pub mod sai { + #[doc = "SAI"] + pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock; #[doc = "SAI"] pub const SAI2: *const RegisterBlock = 0x4040_8000 as *const RegisterBlock; #[doc = "SAI"] @@ -4550,6 +4552,20 @@ pub mod sai { mod blocks; pub use blocks::*; pub type Instance = crate::Instance; + pub type SAI1 = Instance<1>; + impl crate::private::Sealed for SAI1 {} + impl crate::Valid for SAI1 {} + impl SAI1 { + #[doc = r" Acquire a vaild, but possibly aliased, instance."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" See [the struct-level safety documentation](crate::Instance)."] + #[inline] + pub const unsafe fn instance() -> Self { + Instance::new(SAI1) + } + } pub type SAI2 = Instance<2>; impl crate::private::Sealed for SAI2 {} impl crate::Valid for SAI2 {} @@ -4594,40 +4610,13 @@ pub mod sai { } #[doc = r" Returns the instance number `N` for a peripheral instance."] pub fn number(rb: *const RegisterBlock) -> Option { - [(SAI2, 2), (SAI3, 3), (SAI4, 4)] + [(SAI1, 1), (SAI2, 2), (SAI3, 3), (SAI4, 4)] .into_iter() .find(|(ptr, _)| core::ptr::eq(rb, *ptr)) .map(|(_, inst)| inst) } } #[path = "."] -pub mod sai1 { - #[doc = "SAI"] - pub const SAI1: *const RegisterBlock = 0x4040_4000 as *const RegisterBlock; - #[path = "blocks/imxrt1176_cm4/sai1.rs"] - mod blocks; - pub use blocks::*; - pub type Instance = crate::Instance; - pub type SAI1 = Instance<{ crate::SOLE_INSTANCE }>; - impl crate::private::Sealed for SAI1 {} - impl crate::Valid for SAI1 {} - impl SAI1 { - #[doc = r" Acquire a vaild, but possibly aliased, instance."] - #[doc = r""] - #[doc = r" # Safety"] - #[doc = r""] - #[doc = r" See [the struct-level safety documentation](crate::Instance)."] - #[inline] - pub const unsafe fn instance() -> Self { - Instance::new(SAI1) - } - } - #[doc = r" Returns the instance number `N` for a peripheral instance."] - pub fn number(rb: *const RegisterBlock) -> Option { - core::ptr::eq(rb, SAI1).then_some(0) - } -} -#[path = "."] pub mod sema4 { #[doc = "IPS_Semaphores"] pub const SEMA4: *const RegisterBlock = 0x40cc_8000 as *const RegisterBlock; @@ -5645,10 +5634,10 @@ pub struct Instances { pub RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2, pub RTWDOG3: rtwdog::RTWDOG3, pub RTWDOG4: rtwdog::RTWDOG4, + pub SAI1: sai::SAI1, pub SAI2: sai::SAI2, pub SAI3: sai::SAI3, pub SAI4: sai::SAI4, - pub SAI1: sai1::SAI1, pub SEMA4: sema4::SEMA4, pub SEMC: semc::SEMC, pub SNVS: snvs::SNVS, @@ -5851,10 +5840,10 @@ impl Instances { RDC_SEMAPHORE2: rdc_semaphore::RDC_SEMAPHORE2::instance(), RTWDOG3: rtwdog::RTWDOG3::instance(), RTWDOG4: rtwdog::RTWDOG4::instance(), + SAI1: sai::SAI1::instance(), SAI2: sai::SAI2::instance(), SAI3: sai::SAI3::instance(), SAI4: sai::SAI4::instance(), - SAI1: sai1::SAI1::instance(), SEMA4: sema4::SEMA4::instance(), SEMC: semc::SEMC::instance(), SNVS: snvs::SNVS::instance(),