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  1. SystemVerilogCourse SystemVerilogCourse Public

    This is a detailed SystemVerilog course

    SystemVerilog 71 35

  2. UVMCourse UVMCourse Public

    Structured UVM Course

    SystemVerilog 34 14

  3. axi4_avip axi4_avip Public

    SystemVerilog 23 25

  4. apb_avip apb_avip Public

    SystemVerilog 14 9

  5. i3c_avip i3c_avip Public

    Verification IP project for I3C protocol

    SystemVerilog 14 7

  6. spi_avip spi_avip Public

    SystemVerilog 9 5

Repositories

Showing 10 of 17 repositories
  • axi4Lite_avip Public

    This project deals with the axi4Lite protocol

    mbits-mirafra/axi4Lite_avip’s past year of commit activity
    SystemVerilog 6 0 3 0 Updated Nov 15, 2024
  • i3c_avip Public

    Verification IP project for I3C protocol

    mbits-mirafra/i3c_avip’s past year of commit activity
    SystemVerilog 14 7 3 0 Updated Jul 12, 2024
  • digitalDesignCourse Public

    Structured and peer-reviewed course for Digital Design Systems

    mbits-mirafra/digitalDesignCourse’s past year of commit activity
    Verilog 2 MIT 4 0 0 Updated May 31, 2024
  • pulpino__i2c_master__ip_verification Public

    IP Veriification of I2C master using the I3C VIP

    mbits-mirafra/pulpino__i2c_master__ip_verification’s past year of commit activity
    SystemVerilog 4 2 0 0 Updated May 29, 2024
  • axi4_avip Public
    mbits-mirafra/axi4_avip’s past year of commit activity
    SystemVerilog 23 MIT 25 40 0 Updated Apr 8, 2024
  • neovim Public

    This project is created to arrange and align different nvim editor plugins to make the DesignVerification tasks faster.

    mbits-mirafra/neovim’s past year of commit activity
    Lua 1 MIT 0 3 0 Updated Feb 20, 2024
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    mbits-mirafra/verilator’s past year of commit activity
    C++ 0 LGPL-3.0 621 0 0 Updated Feb 11, 2024
  • cpu-lite Public

    CPU Lite is a small CPU designed for instruction purposes.

    mbits-mirafra/cpu-lite’s past year of commit activity
    Python 3 2 0 0 Updated Feb 11, 2024
  • UVMCourse Public

    Structured UVM Course

    mbits-mirafra/UVMCourse’s past year of commit activity
    SystemVerilog 34 14 0 0 Updated Jan 4, 2024
  • SystemVerilogCourse Public

    This is a detailed SystemVerilog course

    mbits-mirafra/SystemVerilogCourse’s past year of commit activity
    SystemVerilog 71 35 0 0 Updated Jan 4, 2024
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