diff --git a/inou/cgen/cgen_verilog.cpp b/inou/cgen/cgen_verilog.cpp
index d3ba492dd..b7e49429f 100644
--- a/inou/cgen/cgen_verilog.cpp
+++ b/inou/cgen/cgen_verilog.cpp
@@ -232,7 +232,7 @@ void Cgen_verilog::process_memory(std::shared_ptr<File_output> fout, Node &node)
     name = absl::StrCat(name, n_rd_ports, "rd_");
     name = absl::StrCat(name, n_wr_ports, "wr");
 
-    //include
+    // include
     fout->prepend(absl::StrCat("`include \"", name, ".v\" \n"));
     fout->append(absl::StrCat(name));
 
@@ -677,6 +677,10 @@ void Cgen_verilog::process_simple_node(std::shared_ptr<File_output> fout, Node &
     final_expr = "'hx";
   }
 
+  if (node.has_color()) {
+    absl::StrAppend(&final_expr, " /* color:", std::to_string(node.get_color()), "*/");
+  }
+
   auto var_it = pin2var.find(dpin.get_compact_class());
   if (var_it == pin2var.end()) {
     pin2expr.emplace(dpin.get_compact_class(), Expr(final_expr, true));
diff --git a/inou/yosys/lgyosys_tolg.cpp b/inou/yosys/lgyosys_tolg.cpp
index 2d31b87a7..82c2078bd 100644
--- a/inou/yosys/lgyosys_tolg.cpp
+++ b/inou/yosys/lgyosys_tolg.cpp
@@ -808,9 +808,7 @@ static void process_cell_drivers_intialization(RTLIL::Module *mod, Lgraph *g) {
             continue;
           }
 
-#ifndef NDEBUG
-          fmt::print("module {} submodule {} has output pin_name {}\n", mod->name.c_str(), cell->type.c_str(), pin_name.c_str());
-#endif
+          // fmt::print("module {} submodule {} has output pin_name {}\n", mod->name.c_str(), cell->type.c_str(), pin_name.c_str());
         }
 
       } else {
@@ -2575,7 +2573,7 @@ struct Yosys2lg_Pass : public Yosys::Pass {
             if (lchunk.width == 0) {
               continue;
             }
-            fmt::print("Assignment to {}\n", lhs_wire->name.c_str());
+            // fmt::print("Assignment to {}\n", lhs_wire->name.c_str());
             driven_signals.insert(lhs_wire->hash());
           }
         }
diff --git a/pass/label/label_synth.cpp b/pass/label/label_synth.cpp
index 93655b9a6..0bd7e39d3 100644
--- a/pass/label/label_synth.cpp
+++ b/pass/label/label_synth.cpp
@@ -190,7 +190,7 @@ void Label_synth::label(Lgraph *g) {
     if (flat_node2id.find(nc) != flat_node2id.end()) {
       n.set_color(flat_node2id[nc]);
     } else {
-      n.set_color(NO_COLOR);
+      n.del_color();
     }
   }