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top_wrapper_utilization_placed.rpt
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top_wrapper_utilization_placed.rpt
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4.1 (lin64) Build 2117270 Tue Jan 30 15:31:13 MST 2018
| Date : Sat Jun 9 09:29:31 2018
| Host : marti-UX330UAK running 64-bit Ubuntu 17.10
| Command : report_utilization -file top_wrapper_utilization_placed.rpt -pb top_wrapper_utilization_placed.pb
| Design : top_wrapper
| Device : 7z010clg400-1
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs | 1517 | 0 | 17600 | 8.62 |
| LUT as Logic | 1399 | 0 | 17600 | 7.95 |
| LUT as Memory | 118 | 0 | 6000 | 1.97 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 118 | 0 | | |
| Slice Registers | 1422 | 0 | 35200 | 4.04 |
| Register as Flip Flop | 1422 | 0 | 35200 | 4.04 |
| Register as Latch | 0 | 0 | 35200 | 0.00 |
| F7 Muxes | 0 | 0 | 8800 | 0.00 |
| F8 Muxes | 0 | 0 | 4400 | 0.00 |
+----------------------------+------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 198 | Yes | Set | - |
| 1224 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| Slice | 494 | 0 | 4400 | 11.23 |
| SLICEL | 303 | 0 | | |
| SLICEM | 191 | 0 | | |
| LUT as Logic | 1399 | 0 | 17600 | 7.95 |
| using O5 output only | 0 | | | |
| using O6 output only | 1046 | | | |
| using O5 and O6 | 353 | | | |
| LUT as Memory | 118 | 0 | 6000 | 1.97 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 118 | 0 | | |
| using O5 output only | 64 | | | |
| using O6 output only | 54 | | | |
| using O5 and O6 | 0 | | | |
| LUT Flip Flop Pairs | 834 | 0 | 17600 | 4.74 |
| fully used LUT-FF pairs | 165 | | | |
| LUT-FF pairs with one unused LUT output | 632 | | | |
| LUT-FF pairs with one unused Flip Flop | 608 | | | |
| Unique Control Sets | 37 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 60 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 |
| RAMB18 | 0 | 0 | 120 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 80 | 0.00 |
+-----------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 0 | 0 | 100 | 0.00 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 130 | 130 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 100 | 0.00 |
+-----------------------------+------+-------+-----------+--------+
6. Clocking
-----------
+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 8 | 0.00 |
+------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+----------+------+----------------------+
| Ref Name | Used | Functional Category |
+----------+------+----------------------+
| FDRE | 1224 | Flop & Latch |
| LUT6 | 644 | LUT |
| LUT3 | 369 | LUT |
| LUT5 | 322 | LUT |
| LUT4 | 243 | LUT |
| FDSE | 198 | Flop & Latch |
| LUT2 | 165 | LUT |
| BIBUF | 130 | IO |
| SRL16E | 77 | Distributed Memory |
| CARRY4 | 74 | CarryLogic |
| SRLC32E | 41 | Distributed Memory |
| LUT1 | 9 | LUT |
| PS7 | 1 | Specialized Resource |
| BUFG | 1 | Clock |
+----------+------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+-----------------------+------+
| Ref Name | Used |
+-----------------------+------+
| top_sha256_ctrl_axi_0 | 1 |
| top_rst_ps7_100M_0 | 1 |
| top_ps7_0 | 1 |
| top_auto_pc_0 | 1 |
+-----------------------+------+