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Commits on Feb 9, 2022

• cxl/mem: Add the cxl_mem driver

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  Ben Widawsky

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• cxl/core/port: Add switch port enumeration

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• cxl/memdev: Add numa_node attribute

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• cxl/pci: Emit device serial number

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• cxl/pci: Implement wait for media active

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• cxl/pci: Retrieve CXL DVSEC memory info

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• cxl/pci: Cache device DVSEC offset

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• cxl/pci: Store component register base in cxlds

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• cxl/core/port: Remove @host argument for dport + decoder enumeration

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• cxl/port: Add a driver for 'struct cxl_port' objects

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• cxl/core: Emit modalias for CXL devices

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• cxl/core/hdm: Add CXL standard decoder enumeration to the core

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• cxl/core: Generalize dport enumeration in the core

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• cxl/pci: Rename pci.h to cxlpci.h

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• cxl/port: Up-level cxl_add_dport() locking requirements to the caller

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• cxl/pmem: Introduce a find_cxl_root() helper

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• cxl/port: Introduce cxl_port_to_pci_bus()

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• cxl/core/port: Use dedicated lock for decoder target list

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• cxl: Prove CXL locking

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• cxl/core: Track port depth

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• cxl/core/port: Make passthrough decoder init implicit

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• cxl/core: Fix cxl_probe_component_regs() error message

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• cxl/core/port: Clarify decoder creation

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• cxl/core: Convert decoder range to resource

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• cxl/decoder: Hide physical address information from non-root

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• cxl/core/port: Rename bus.c to port.c

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• cxl: Introduce module_cxl_driver

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• cxl/acpi: Map component registers for Root Ports

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• cxl/pci: Add new DVSEC definitions

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• cxl: Flesh out register names

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• cxl/pci: Defer mailbox status checks to command timeouts

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• cxl/pci: Implement Interface Ready Timeout

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• cxl: Rename CXL_MEM to CXL_PCI

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Commits on Jan 30, 2022

• Linux 5.17-rc2

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• Merge tag 'irq_urgent_for_v5.17_rc2_p2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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