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iqs269a.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Azoteq IQS269A Capacitive Touch Controller
*
* Copyright (C) 2020 Jeff LaBundy <jeff@labundy.com>
*
* This driver registers up to 3 input devices: one representing capacitive or
* inductive keys as well as Hall-effect switches, and one for each of the two
* axial sliders presented by the device.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/i2c.h>
#include <linux/input.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#define IQS269_VER_INFO 0x00
#define IQS269_VER_INFO_PROD_NUM 0x4F
#define IQS269_SYS_FLAGS 0x02
#define IQS269_SYS_FLAGS_SHOW_RESET BIT(15)
#define IQS269_SYS_FLAGS_PWR_MODE_MASK GENMASK(12, 11)
#define IQS269_SYS_FLAGS_PWR_MODE_SHIFT 11
#define IQS269_SYS_FLAGS_IN_ATI BIT(10)
#define IQS269_CHx_COUNTS 0x08
#define IQS269_SLIDER_X 0x30
#define IQS269_CAL_DATA_A 0x35
#define IQS269_CAL_DATA_A_HALL_BIN_L_MASK GENMASK(15, 12)
#define IQS269_CAL_DATA_A_HALL_BIN_L_SHIFT 12
#define IQS269_CAL_DATA_A_HALL_BIN_R_MASK GENMASK(11, 8)
#define IQS269_CAL_DATA_A_HALL_BIN_R_SHIFT 8
#define IQS269_SYS_SETTINGS 0x80
#define IQS269_SYS_SETTINGS_CLK_DIV BIT(15)
#define IQS269_SYS_SETTINGS_ULP_AUTO BIT(14)
#define IQS269_SYS_SETTINGS_DIS_AUTO BIT(13)
#define IQS269_SYS_SETTINGS_PWR_MODE_MASK GENMASK(12, 11)
#define IQS269_SYS_SETTINGS_PWR_MODE_SHIFT 11
#define IQS269_SYS_SETTINGS_PWR_MODE_MAX 3
#define IQS269_SYS_SETTINGS_ULP_UPDATE_MASK GENMASK(10, 8)
#define IQS269_SYS_SETTINGS_ULP_UPDATE_SHIFT 8
#define IQS269_SYS_SETTINGS_ULP_UPDATE_MAX 7
#define IQS269_SYS_SETTINGS_RESEED_OFFSET BIT(6)
#define IQS269_SYS_SETTINGS_EVENT_MODE BIT(5)
#define IQS269_SYS_SETTINGS_EVENT_MODE_LP BIT(4)
#define IQS269_SYS_SETTINGS_REDO_ATI BIT(2)
#define IQS269_SYS_SETTINGS_ACK_RESET BIT(0)
#define IQS269_FILT_STR_LP_LTA_MASK GENMASK(7, 6)
#define IQS269_FILT_STR_LP_LTA_SHIFT 6
#define IQS269_FILT_STR_LP_CNT_MASK GENMASK(5, 4)
#define IQS269_FILT_STR_LP_CNT_SHIFT 4
#define IQS269_FILT_STR_NP_LTA_MASK GENMASK(3, 2)
#define IQS269_FILT_STR_NP_LTA_SHIFT 2
#define IQS269_FILT_STR_NP_CNT_MASK GENMASK(1, 0)
#define IQS269_FILT_STR_MAX 3
#define IQS269_EVENT_MASK_SYS BIT(6)
#define IQS269_EVENT_MASK_DEEP BIT(2)
#define IQS269_EVENT_MASK_TOUCH BIT(1)
#define IQS269_EVENT_MASK_PROX BIT(0)
#define IQS269_RATE_NP_MS_MAX 255
#define IQS269_RATE_LP_MS_MAX 255
#define IQS269_RATE_ULP_MS_MAX 4080
#define IQS269_TIMEOUT_PWR_MS_MAX 130560
#define IQS269_TIMEOUT_LTA_MS_MAX 130560
#define IQS269_MISC_A_ATI_BAND_DISABLE BIT(15)
#define IQS269_MISC_A_ATI_LP_ONLY BIT(14)
#define IQS269_MISC_A_ATI_BAND_TIGHTEN BIT(13)
#define IQS269_MISC_A_FILT_DISABLE BIT(12)
#define IQS269_MISC_A_GPIO3_SELECT_MASK GENMASK(10, 8)
#define IQS269_MISC_A_GPIO3_SELECT_SHIFT 8
#define IQS269_MISC_A_DUAL_DIR BIT(6)
#define IQS269_MISC_A_TX_FREQ_MASK GENMASK(5, 4)
#define IQS269_MISC_A_TX_FREQ_SHIFT 4
#define IQS269_MISC_A_TX_FREQ_MAX 3
#define IQS269_MISC_A_GLOBAL_CAP_SIZE BIT(0)
#define IQS269_MISC_B_RESEED_UI_SEL_MASK GENMASK(7, 6)
#define IQS269_MISC_B_RESEED_UI_SEL_SHIFT 6
#define IQS269_MISC_B_RESEED_UI_SEL_MAX 3
#define IQS269_MISC_B_TRACKING_UI_ENABLE BIT(4)
#define IQS269_MISC_B_FILT_STR_SLIDER GENMASK(1, 0)
#define IQS269_CHx_SETTINGS 0x8C
#define IQS269_CHx_ENG_A_MEAS_CAP_SIZE BIT(15)
#define IQS269_CHx_ENG_A_RX_GND_INACTIVE BIT(13)
#define IQS269_CHx_ENG_A_LOCAL_CAP_SIZE BIT(12)
#define IQS269_CHx_ENG_A_ATI_MODE_MASK GENMASK(9, 8)
#define IQS269_CHx_ENG_A_ATI_MODE_SHIFT 8
#define IQS269_CHx_ENG_A_ATI_MODE_MAX 3
#define IQS269_CHx_ENG_A_INV_LOGIC BIT(7)
#define IQS269_CHx_ENG_A_PROJ_BIAS_MASK GENMASK(6, 5)
#define IQS269_CHx_ENG_A_PROJ_BIAS_SHIFT 5
#define IQS269_CHx_ENG_A_PROJ_BIAS_MAX 3
#define IQS269_CHx_ENG_A_SENSE_MODE_MASK GENMASK(3, 0)
#define IQS269_CHx_ENG_A_SENSE_MODE_MAX 15
#define IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE BIT(13)
#define IQS269_CHx_ENG_B_SENSE_FREQ_MASK GENMASK(10, 9)
#define IQS269_CHx_ENG_B_SENSE_FREQ_SHIFT 9
#define IQS269_CHx_ENG_B_SENSE_FREQ_MAX 3
#define IQS269_CHx_ENG_B_STATIC_ENABLE BIT(8)
#define IQS269_CHx_ENG_B_ATI_BASE_MASK GENMASK(7, 6)
#define IQS269_CHx_ENG_B_ATI_BASE_75 0x00
#define IQS269_CHx_ENG_B_ATI_BASE_100 0x40
#define IQS269_CHx_ENG_B_ATI_BASE_150 0x80
#define IQS269_CHx_ENG_B_ATI_BASE_200 0xC0
#define IQS269_CHx_ENG_B_ATI_TARGET_MASK GENMASK(5, 0)
#define IQS269_CHx_ENG_B_ATI_TARGET_MAX 2016
#define IQS269_CHx_WEIGHT_MAX 255
#define IQS269_CHx_THRESH_MAX 255
#define IQS269_CHx_HYST_DEEP_MASK GENMASK(7, 4)
#define IQS269_CHx_HYST_DEEP_SHIFT 4
#define IQS269_CHx_HYST_TOUCH_MASK GENMASK(3, 0)
#define IQS269_CHx_HYST_MAX 15
#define IQS269_CHx_HALL_INACTIVE 6
#define IQS269_CHx_HALL_ACTIVE 7
#define IQS269_HALL_PAD_R BIT(0)
#define IQS269_HALL_PAD_L BIT(1)
#define IQS269_HALL_PAD_INV BIT(6)
#define IQS269_HALL_UI 0xF5
#define IQS269_HALL_UI_ENABLE BIT(15)
#define IQS269_MAX_REG 0xFF
#define IQS269_NUM_CH 8
#define IQS269_NUM_SL 2
#define IQS269_ATI_POLL_SLEEP_US (iqs269->delay_mult * 10000)
#define IQS269_ATI_POLL_TIMEOUT_US (iqs269->delay_mult * 500000)
#define IQS269_ATI_STABLE_DELAY_MS (iqs269->delay_mult * 150)
#define IQS269_PWR_MODE_POLL_SLEEP_US IQS269_ATI_POLL_SLEEP_US
#define IQS269_PWR_MODE_POLL_TIMEOUT_US IQS269_ATI_POLL_TIMEOUT_US
#define iqs269_irq_wait() usleep_range(100, 150)
enum iqs269_local_cap_size {
IQS269_LOCAL_CAP_SIZE_0,
IQS269_LOCAL_CAP_SIZE_GLOBAL_ONLY,
IQS269_LOCAL_CAP_SIZE_GLOBAL_0pF5,
};
enum iqs269_st_offs {
IQS269_ST_OFFS_PROX,
IQS269_ST_OFFS_DIR,
IQS269_ST_OFFS_TOUCH,
IQS269_ST_OFFS_DEEP,
};
enum iqs269_th_offs {
IQS269_TH_OFFS_PROX,
IQS269_TH_OFFS_TOUCH,
IQS269_TH_OFFS_DEEP,
};
enum iqs269_event_id {
IQS269_EVENT_PROX_DN,
IQS269_EVENT_PROX_UP,
IQS269_EVENT_TOUCH_DN,
IQS269_EVENT_TOUCH_UP,
IQS269_EVENT_DEEP_DN,
IQS269_EVENT_DEEP_UP,
};
struct iqs269_switch_desc {
unsigned int code;
bool enabled;
};
struct iqs269_event_desc {
const char *name;
enum iqs269_st_offs st_offs;
enum iqs269_th_offs th_offs;
bool dir_up;
u8 mask;
};
static const struct iqs269_event_desc iqs269_events[] = {
[IQS269_EVENT_PROX_DN] = {
.name = "event-prox",
.st_offs = IQS269_ST_OFFS_PROX,
.th_offs = IQS269_TH_OFFS_PROX,
.mask = IQS269_EVENT_MASK_PROX,
},
[IQS269_EVENT_PROX_UP] = {
.name = "event-prox-alt",
.st_offs = IQS269_ST_OFFS_PROX,
.th_offs = IQS269_TH_OFFS_PROX,
.dir_up = true,
.mask = IQS269_EVENT_MASK_PROX,
},
[IQS269_EVENT_TOUCH_DN] = {
.name = "event-touch",
.st_offs = IQS269_ST_OFFS_TOUCH,
.th_offs = IQS269_TH_OFFS_TOUCH,
.mask = IQS269_EVENT_MASK_TOUCH,
},
[IQS269_EVENT_TOUCH_UP] = {
.name = "event-touch-alt",
.st_offs = IQS269_ST_OFFS_TOUCH,
.th_offs = IQS269_TH_OFFS_TOUCH,
.dir_up = true,
.mask = IQS269_EVENT_MASK_TOUCH,
},
[IQS269_EVENT_DEEP_DN] = {
.name = "event-deep",
.st_offs = IQS269_ST_OFFS_DEEP,
.th_offs = IQS269_TH_OFFS_DEEP,
.mask = IQS269_EVENT_MASK_DEEP,
},
[IQS269_EVENT_DEEP_UP] = {
.name = "event-deep-alt",
.st_offs = IQS269_ST_OFFS_DEEP,
.th_offs = IQS269_TH_OFFS_DEEP,
.dir_up = true,
.mask = IQS269_EVENT_MASK_DEEP,
},
};
struct iqs269_ver_info {
u8 prod_num;
u8 sw_num;
u8 hw_num;
u8 padding;
} __packed;
struct iqs269_sys_reg {
__be16 general;
u8 active;
u8 filter;
u8 reseed;
u8 event_mask;
u8 rate_np;
u8 rate_lp;
u8 rate_ulp;
u8 timeout_pwr;
u8 timeout_rdy;
u8 timeout_lta;
__be16 misc_a;
__be16 misc_b;
u8 blocking;
u8 padding;
u8 slider_select[IQS269_NUM_SL];
u8 timeout_tap;
u8 timeout_swipe;
u8 thresh_swipe;
u8 redo_ati;
} __packed;
struct iqs269_ch_reg {
u8 rx_enable;
u8 tx_enable;
__be16 engine_a;
__be16 engine_b;
__be16 ati_comp;
u8 thresh[3];
u8 hyst;
u8 assoc_select;
u8 assoc_weight;
} __packed;
struct iqs269_flags {
__be16 system;
u8 gesture;
u8 padding;
u8 states[4];
} __packed;
struct iqs269_private {
struct i2c_client *client;
struct regmap *regmap;
struct mutex lock;
struct iqs269_switch_desc switches[ARRAY_SIZE(iqs269_events)];
struct iqs269_ch_reg ch_reg[IQS269_NUM_CH];
struct iqs269_sys_reg sys_reg;
struct input_dev *keypad;
struct input_dev *slider[IQS269_NUM_SL];
unsigned int keycode[ARRAY_SIZE(iqs269_events) * IQS269_NUM_CH];
unsigned int suspend_mode;
unsigned int delay_mult;
unsigned int ch_num;
bool hall_enable;
bool ati_current;
};
static int iqs269_ati_mode_set(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int mode)
{
u16 engine_a;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
if (mode > IQS269_CHx_ENG_A_ATI_MODE_MAX)
return -EINVAL;
mutex_lock(&iqs269->lock);
engine_a = be16_to_cpu(iqs269->ch_reg[ch_num].engine_a);
engine_a &= ~IQS269_CHx_ENG_A_ATI_MODE_MASK;
engine_a |= (mode << IQS269_CHx_ENG_A_ATI_MODE_SHIFT);
iqs269->ch_reg[ch_num].engine_a = cpu_to_be16(engine_a);
iqs269->ati_current = false;
mutex_unlock(&iqs269->lock);
return 0;
}
static int iqs269_ati_mode_get(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int *mode)
{
u16 engine_a;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
mutex_lock(&iqs269->lock);
engine_a = be16_to_cpu(iqs269->ch_reg[ch_num].engine_a);
mutex_unlock(&iqs269->lock);
engine_a &= IQS269_CHx_ENG_A_ATI_MODE_MASK;
*mode = (engine_a >> IQS269_CHx_ENG_A_ATI_MODE_SHIFT);
return 0;
}
static int iqs269_ati_base_set(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int base)
{
u16 engine_b;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
switch (base) {
case 75:
base = IQS269_CHx_ENG_B_ATI_BASE_75;
break;
case 100:
base = IQS269_CHx_ENG_B_ATI_BASE_100;
break;
case 150:
base = IQS269_CHx_ENG_B_ATI_BASE_150;
break;
case 200:
base = IQS269_CHx_ENG_B_ATI_BASE_200;
break;
default:
return -EINVAL;
}
mutex_lock(&iqs269->lock);
engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
engine_b &= ~IQS269_CHx_ENG_B_ATI_BASE_MASK;
engine_b |= base;
iqs269->ch_reg[ch_num].engine_b = cpu_to_be16(engine_b);
iqs269->ati_current = false;
mutex_unlock(&iqs269->lock);
return 0;
}
static int iqs269_ati_base_get(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int *base)
{
u16 engine_b;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
mutex_lock(&iqs269->lock);
engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
mutex_unlock(&iqs269->lock);
switch (engine_b & IQS269_CHx_ENG_B_ATI_BASE_MASK) {
case IQS269_CHx_ENG_B_ATI_BASE_75:
*base = 75;
return 0;
case IQS269_CHx_ENG_B_ATI_BASE_100:
*base = 100;
return 0;
case IQS269_CHx_ENG_B_ATI_BASE_150:
*base = 150;
return 0;
case IQS269_CHx_ENG_B_ATI_BASE_200:
*base = 200;
return 0;
default:
return -EINVAL;
}
}
static int iqs269_ati_target_set(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int target)
{
u16 engine_b;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
if (target > IQS269_CHx_ENG_B_ATI_TARGET_MAX)
return -EINVAL;
mutex_lock(&iqs269->lock);
engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
engine_b &= ~IQS269_CHx_ENG_B_ATI_TARGET_MASK;
engine_b |= target / 32;
iqs269->ch_reg[ch_num].engine_b = cpu_to_be16(engine_b);
iqs269->ati_current = false;
mutex_unlock(&iqs269->lock);
return 0;
}
static int iqs269_ati_target_get(struct iqs269_private *iqs269,
unsigned int ch_num, unsigned int *target)
{
u16 engine_b;
if (ch_num >= IQS269_NUM_CH)
return -EINVAL;
mutex_lock(&iqs269->lock);
engine_b = be16_to_cpu(iqs269->ch_reg[ch_num].engine_b);
mutex_unlock(&iqs269->lock);
*target = (engine_b & IQS269_CHx_ENG_B_ATI_TARGET_MASK) * 32;
return 0;
}
static int iqs269_parse_mask(const struct fwnode_handle *fwnode,
const char *propname, u8 *mask)
{
unsigned int val[IQS269_NUM_CH];
int count, error, i;
count = fwnode_property_count_u32(fwnode, propname);
if (count < 0)
return 0;
if (count > IQS269_NUM_CH)
return -EINVAL;
error = fwnode_property_read_u32_array(fwnode, propname, val, count);
if (error)
return error;
*mask = 0;
for (i = 0; i < count; i++) {
if (val[i] >= IQS269_NUM_CH)
return -EINVAL;
*mask |= BIT(val[i]);
}
return 0;
}
static int iqs269_parse_chan(struct iqs269_private *iqs269,
const struct fwnode_handle *ch_node)
{
struct i2c_client *client = iqs269->client;
struct fwnode_handle *ev_node;
struct iqs269_ch_reg *ch_reg;
u16 engine_a, engine_b;
unsigned int reg, val;
int error, i;
error = fwnode_property_read_u32(ch_node, "reg", ®);
if (error) {
dev_err(&client->dev, "Failed to read channel number: %d\n",
error);
return error;
} else if (reg >= IQS269_NUM_CH) {
dev_err(&client->dev, "Invalid channel number: %u\n", reg);
return -EINVAL;
}
iqs269->sys_reg.active |= BIT(reg);
if (!fwnode_property_present(ch_node, "azoteq,reseed-disable"))
iqs269->sys_reg.reseed |= BIT(reg);
if (fwnode_property_present(ch_node, "azoteq,blocking-enable"))
iqs269->sys_reg.blocking |= BIT(reg);
if (fwnode_property_present(ch_node, "azoteq,slider0-select"))
iqs269->sys_reg.slider_select[0] |= BIT(reg);
if (fwnode_property_present(ch_node, "azoteq,slider1-select"))
iqs269->sys_reg.slider_select[1] |= BIT(reg);
ch_reg = &iqs269->ch_reg[reg];
error = regmap_raw_read(iqs269->regmap,
IQS269_CHx_SETTINGS + reg * sizeof(*ch_reg) / 2,
ch_reg, sizeof(*ch_reg));
if (error)
return error;
error = iqs269_parse_mask(ch_node, "azoteq,rx-enable",
&ch_reg->rx_enable);
if (error) {
dev_err(&client->dev, "Invalid channel %u RX enable mask: %d\n",
reg, error);
return error;
}
error = iqs269_parse_mask(ch_node, "azoteq,tx-enable",
&ch_reg->tx_enable);
if (error) {
dev_err(&client->dev, "Invalid channel %u TX enable mask: %d\n",
reg, error);
return error;
}
engine_a = be16_to_cpu(ch_reg->engine_a);
engine_b = be16_to_cpu(ch_reg->engine_b);
engine_a |= IQS269_CHx_ENG_A_MEAS_CAP_SIZE;
if (fwnode_property_present(ch_node, "azoteq,meas-cap-decrease"))
engine_a &= ~IQS269_CHx_ENG_A_MEAS_CAP_SIZE;
engine_a |= IQS269_CHx_ENG_A_RX_GND_INACTIVE;
if (fwnode_property_present(ch_node, "azoteq,rx-float-inactive"))
engine_a &= ~IQS269_CHx_ENG_A_RX_GND_INACTIVE;
engine_a &= ~IQS269_CHx_ENG_A_LOCAL_CAP_SIZE;
engine_b &= ~IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE;
if (!fwnode_property_read_u32(ch_node, "azoteq,local-cap-size", &val)) {
switch (val) {
case IQS269_LOCAL_CAP_SIZE_0:
break;
case IQS269_LOCAL_CAP_SIZE_GLOBAL_0pF5:
engine_a |= IQS269_CHx_ENG_A_LOCAL_CAP_SIZE;
fallthrough;
case IQS269_LOCAL_CAP_SIZE_GLOBAL_ONLY:
engine_b |= IQS269_CHx_ENG_B_LOCAL_CAP_ENABLE;
break;
default:
dev_err(&client->dev,
"Invalid channel %u local cap. size: %u\n", reg,
val);
return -EINVAL;
}
}
engine_a &= ~IQS269_CHx_ENG_A_INV_LOGIC;
if (fwnode_property_present(ch_node, "azoteq,invert-enable"))
engine_a |= IQS269_CHx_ENG_A_INV_LOGIC;
if (!fwnode_property_read_u32(ch_node, "azoteq,proj-bias", &val)) {
if (val > IQS269_CHx_ENG_A_PROJ_BIAS_MAX) {
dev_err(&client->dev,
"Invalid channel %u bias current: %u\n", reg,
val);
return -EINVAL;
}
engine_a &= ~IQS269_CHx_ENG_A_PROJ_BIAS_MASK;
engine_a |= (val << IQS269_CHx_ENG_A_PROJ_BIAS_SHIFT);
}
if (!fwnode_property_read_u32(ch_node, "azoteq,sense-mode", &val)) {
if (val > IQS269_CHx_ENG_A_SENSE_MODE_MAX) {
dev_err(&client->dev,
"Invalid channel %u sensing mode: %u\n", reg,
val);
return -EINVAL;
}
engine_a &= ~IQS269_CHx_ENG_A_SENSE_MODE_MASK;
engine_a |= val;
}
if (!fwnode_property_read_u32(ch_node, "azoteq,sense-freq", &val)) {
if (val > IQS269_CHx_ENG_B_SENSE_FREQ_MAX) {
dev_err(&client->dev,
"Invalid channel %u sensing frequency: %u\n",
reg, val);
return -EINVAL;
}
engine_b &= ~IQS269_CHx_ENG_B_SENSE_FREQ_MASK;
engine_b |= (val << IQS269_CHx_ENG_B_SENSE_FREQ_SHIFT);
}
engine_b &= ~IQS269_CHx_ENG_B_STATIC_ENABLE;
if (fwnode_property_present(ch_node, "azoteq,static-enable"))
engine_b |= IQS269_CHx_ENG_B_STATIC_ENABLE;
ch_reg->engine_a = cpu_to_be16(engine_a);
ch_reg->engine_b = cpu_to_be16(engine_b);
if (!fwnode_property_read_u32(ch_node, "azoteq,ati-mode", &val)) {
error = iqs269_ati_mode_set(iqs269, reg, val);
if (error) {
dev_err(&client->dev,
"Invalid channel %u ATI mode: %u\n", reg, val);
return error;
}
}
if (!fwnode_property_read_u32(ch_node, "azoteq,ati-base", &val)) {
error = iqs269_ati_base_set(iqs269, reg, val);
if (error) {
dev_err(&client->dev,
"Invalid channel %u ATI base: %u\n", reg, val);
return error;
}
}
if (!fwnode_property_read_u32(ch_node, "azoteq,ati-target", &val)) {
error = iqs269_ati_target_set(iqs269, reg, val);
if (error) {
dev_err(&client->dev,
"Invalid channel %u ATI target: %u\n", reg,
val);
return error;
}
}
error = iqs269_parse_mask(ch_node, "azoteq,assoc-select",
&ch_reg->assoc_select);
if (error) {
dev_err(&client->dev, "Invalid channel %u association: %d\n",
reg, error);
return error;
}
if (!fwnode_property_read_u32(ch_node, "azoteq,assoc-weight", &val)) {
if (val > IQS269_CHx_WEIGHT_MAX) {
dev_err(&client->dev,
"Invalid channel %u associated weight: %u\n",
reg, val);
return -EINVAL;
}
ch_reg->assoc_weight = val;
}
for (i = 0; i < ARRAY_SIZE(iqs269_events); i++) {
ev_node = fwnode_get_named_child_node(ch_node,
iqs269_events[i].name);
if (!ev_node)
continue;
if (!fwnode_property_read_u32(ev_node, "azoteq,thresh", &val)) {
if (val > IQS269_CHx_THRESH_MAX) {
dev_err(&client->dev,
"Invalid channel %u threshold: %u\n",
reg, val);
return -EINVAL;
}
ch_reg->thresh[iqs269_events[i].th_offs] = val;
}
if (!fwnode_property_read_u32(ev_node, "azoteq,hyst", &val)) {
u8 *hyst = &ch_reg->hyst;
if (val > IQS269_CHx_HYST_MAX) {
dev_err(&client->dev,
"Invalid channel %u hysteresis: %u\n",
reg, val);
return -EINVAL;
}
if (i == IQS269_EVENT_DEEP_DN ||
i == IQS269_EVENT_DEEP_UP) {
*hyst &= ~IQS269_CHx_HYST_DEEP_MASK;
*hyst |= (val << IQS269_CHx_HYST_DEEP_SHIFT);
} else if (i == IQS269_EVENT_TOUCH_DN ||
i == IQS269_EVENT_TOUCH_UP) {
*hyst &= ~IQS269_CHx_HYST_TOUCH_MASK;
*hyst |= val;
}
}
if (fwnode_property_read_u32(ev_node, "linux,code", &val))
continue;
switch (reg) {
case IQS269_CHx_HALL_ACTIVE:
if (iqs269->hall_enable) {
iqs269->switches[i].code = val;
iqs269->switches[i].enabled = true;
}
fallthrough;
case IQS269_CHx_HALL_INACTIVE:
if (iqs269->hall_enable)
break;
fallthrough;
default:
iqs269->keycode[i * IQS269_NUM_CH + reg] = val;
}
iqs269->sys_reg.event_mask &= ~iqs269_events[i].mask;
}
return 0;
}
static int iqs269_parse_prop(struct iqs269_private *iqs269)
{
struct iqs269_sys_reg *sys_reg = &iqs269->sys_reg;
struct i2c_client *client = iqs269->client;
struct fwnode_handle *ch_node;
u16 general, misc_a, misc_b;
unsigned int val;
int error;
iqs269->hall_enable = device_property_present(&client->dev,
"azoteq,hall-enable");
if (!device_property_read_u32(&client->dev, "azoteq,suspend-mode",
&val)) {
if (val > IQS269_SYS_SETTINGS_PWR_MODE_MAX) {
dev_err(&client->dev, "Invalid suspend mode: %u\n",
val);
return -EINVAL;
}
iqs269->suspend_mode = val;
}
error = regmap_raw_read(iqs269->regmap, IQS269_SYS_SETTINGS, sys_reg,
sizeof(*sys_reg));
if (error)
return error;
if (!device_property_read_u32(&client->dev, "azoteq,filt-str-lp-lta",
&val)) {
if (val > IQS269_FILT_STR_MAX) {
dev_err(&client->dev, "Invalid filter strength: %u\n",
val);
return -EINVAL;
}
sys_reg->filter &= ~IQS269_FILT_STR_LP_LTA_MASK;
sys_reg->filter |= (val << IQS269_FILT_STR_LP_LTA_SHIFT);
}
if (!device_property_read_u32(&client->dev, "azoteq,filt-str-lp-cnt",
&val)) {
if (val > IQS269_FILT_STR_MAX) {
dev_err(&client->dev, "Invalid filter strength: %u\n",
val);
return -EINVAL;
}
sys_reg->filter &= ~IQS269_FILT_STR_LP_CNT_MASK;
sys_reg->filter |= (val << IQS269_FILT_STR_LP_CNT_SHIFT);
}
if (!device_property_read_u32(&client->dev, "azoteq,filt-str-np-lta",
&val)) {
if (val > IQS269_FILT_STR_MAX) {
dev_err(&client->dev, "Invalid filter strength: %u\n",
val);
return -EINVAL;
}
sys_reg->filter &= ~IQS269_FILT_STR_NP_LTA_MASK;
sys_reg->filter |= (val << IQS269_FILT_STR_NP_LTA_SHIFT);
}
if (!device_property_read_u32(&client->dev, "azoteq,filt-str-np-cnt",
&val)) {
if (val > IQS269_FILT_STR_MAX) {
dev_err(&client->dev, "Invalid filter strength: %u\n",
val);
return -EINVAL;
}
sys_reg->filter &= ~IQS269_FILT_STR_NP_CNT_MASK;
sys_reg->filter |= val;
}
if (!device_property_read_u32(&client->dev, "azoteq,rate-np-ms",
&val)) {
if (val > IQS269_RATE_NP_MS_MAX) {
dev_err(&client->dev, "Invalid report rate: %u\n", val);
return -EINVAL;
}
sys_reg->rate_np = val;
}
if (!device_property_read_u32(&client->dev, "azoteq,rate-lp-ms",
&val)) {
if (val > IQS269_RATE_LP_MS_MAX) {
dev_err(&client->dev, "Invalid report rate: %u\n", val);
return -EINVAL;
}
sys_reg->rate_lp = val;
}
if (!device_property_read_u32(&client->dev, "azoteq,rate-ulp-ms",
&val)) {
if (val > IQS269_RATE_ULP_MS_MAX) {
dev_err(&client->dev, "Invalid report rate: %u\n", val);
return -EINVAL;
}
sys_reg->rate_ulp = val / 16;
}
if (!device_property_read_u32(&client->dev, "azoteq,timeout-pwr-ms",
&val)) {
if (val > IQS269_TIMEOUT_PWR_MS_MAX) {
dev_err(&client->dev, "Invalid timeout: %u\n", val);
return -EINVAL;
}
sys_reg->timeout_pwr = val / 512;
}
if (!device_property_read_u32(&client->dev, "azoteq,timeout-lta-ms",
&val)) {
if (val > IQS269_TIMEOUT_LTA_MS_MAX) {
dev_err(&client->dev, "Invalid timeout: %u\n", val);
return -EINVAL;
}
sys_reg->timeout_lta = val / 512;
}
misc_a = be16_to_cpu(sys_reg->misc_a);
misc_b = be16_to_cpu(sys_reg->misc_b);
misc_a &= ~IQS269_MISC_A_ATI_BAND_DISABLE;
if (device_property_present(&client->dev, "azoteq,ati-band-disable"))
misc_a |= IQS269_MISC_A_ATI_BAND_DISABLE;
misc_a &= ~IQS269_MISC_A_ATI_LP_ONLY;
if (device_property_present(&client->dev, "azoteq,ati-lp-only"))
misc_a |= IQS269_MISC_A_ATI_LP_ONLY;
misc_a &= ~IQS269_MISC_A_ATI_BAND_TIGHTEN;
if (device_property_present(&client->dev, "azoteq,ati-band-tighten"))
misc_a |= IQS269_MISC_A_ATI_BAND_TIGHTEN;
misc_a &= ~IQS269_MISC_A_FILT_DISABLE;
if (device_property_present(&client->dev, "azoteq,filt-disable"))
misc_a |= IQS269_MISC_A_FILT_DISABLE;
if (!device_property_read_u32(&client->dev, "azoteq,gpio3-select",
&val)) {
if (val >= IQS269_NUM_CH) {
dev_err(&client->dev, "Invalid GPIO3 selection: %u\n",
val);
return -EINVAL;
}
misc_a &= ~IQS269_MISC_A_GPIO3_SELECT_MASK;
misc_a |= (val << IQS269_MISC_A_GPIO3_SELECT_SHIFT);
}
misc_a &= ~IQS269_MISC_A_DUAL_DIR;
if (device_property_present(&client->dev, "azoteq,dual-direction"))
misc_a |= IQS269_MISC_A_DUAL_DIR;
if (!device_property_read_u32(&client->dev, "azoteq,tx-freq", &val)) {
if (val > IQS269_MISC_A_TX_FREQ_MAX) {
dev_err(&client->dev,
"Invalid excitation frequency: %u\n", val);
return -EINVAL;
}
misc_a &= ~IQS269_MISC_A_TX_FREQ_MASK;
misc_a |= (val << IQS269_MISC_A_TX_FREQ_SHIFT);
}
misc_a &= ~IQS269_MISC_A_GLOBAL_CAP_SIZE;
if (device_property_present(&client->dev, "azoteq,global-cap-increase"))
misc_a |= IQS269_MISC_A_GLOBAL_CAP_SIZE;
if (!device_property_read_u32(&client->dev, "azoteq,reseed-select",
&val)) {
if (val > IQS269_MISC_B_RESEED_UI_SEL_MAX) {
dev_err(&client->dev, "Invalid reseed selection: %u\n",
val);
return -EINVAL;
}
misc_b &= ~IQS269_MISC_B_RESEED_UI_SEL_MASK;
misc_b |= (val << IQS269_MISC_B_RESEED_UI_SEL_SHIFT);
}
misc_b &= ~IQS269_MISC_B_TRACKING_UI_ENABLE;
if (device_property_present(&client->dev, "azoteq,tracking-enable"))
misc_b |= IQS269_MISC_B_TRACKING_UI_ENABLE;
if (!device_property_read_u32(&client->dev, "azoteq,filt-str-slider",
&val)) {
if (val > IQS269_FILT_STR_MAX) {
dev_err(&client->dev, "Invalid filter strength: %u\n",
val);
return -EINVAL;
}
misc_b &= ~IQS269_MISC_B_FILT_STR_SLIDER;
misc_b |= val;
}
sys_reg->misc_a = cpu_to_be16(misc_a);
sys_reg->misc_b = cpu_to_be16(misc_b);
sys_reg->active = 0;
sys_reg->reseed = 0;
sys_reg->blocking = 0;
sys_reg->slider_select[0] = 0;
sys_reg->slider_select[1] = 0;
sys_reg->event_mask = ~((u8)IQS269_EVENT_MASK_SYS);
device_for_each_child_node(&client->dev, ch_node) {
error = iqs269_parse_chan(iqs269, ch_node);
if (error) {
fwnode_handle_put(ch_node);
return error;
}
}
/*
* Volunteer all active channels to participate in ATI when REDO-ATI is
* manually triggered.
*/
sys_reg->redo_ati = sys_reg->active;
general = be16_to_cpu(sys_reg->general);
if (device_property_present(&client->dev, "azoteq,clk-div")) {
general |= IQS269_SYS_SETTINGS_CLK_DIV;
iqs269->delay_mult = 4;
} else {
general &= ~IQS269_SYS_SETTINGS_CLK_DIV;
iqs269->delay_mult = 1;
}
/*
* Configure the device to automatically switch between normal and low-
* power modes as a function of sensing activity. Ultra-low-power mode,
* if enabled, is reserved for suspend.
*/
general &= ~IQS269_SYS_SETTINGS_ULP_AUTO;
general &= ~IQS269_SYS_SETTINGS_DIS_AUTO;
general &= ~IQS269_SYS_SETTINGS_PWR_MODE_MASK;
if (!device_property_read_u32(&client->dev, "azoteq,ulp-update",