Verilog library for ASIC and FPGA designers

The USRP™ Hardware Driver Repository

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …

PACoGen: Posit Arithmetic Core Generator

A place to keep my synthesizable verilog examples.

Wrappers for open source FPU hardware implementations.

Project aimed at implementing floating point operators using the DSP48E1 slice.

Efficient Multiple Constant Multiplication Using DSP Blocks in Xilinx FPGAs

HDL of everything