rtl: Use negedge FF at end of scan chain for better hold margin

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Author: smunaut

src/base.sdc

@@ -2,13 +2,13 @@
 create_clock -name clk_scan_in -period 5 [get_ports {clk_in}]
 create_generated_clock -name clk_scan_out -source clk_in -combinational [get_ports {clk_out}]
 
-# Scan chain input  1.9 ns setup time, -0.1 ns hold time
-set_input_delay  -min -0.1 -clock [get_clocks clk_scan_in]  [get_ports {data_in}] 
-set_input_delay  -max  1.9 -clock [get_clocks clk_scan_in]  [get_ports {data_in}] 
+# Scan chain input  0.5 ns setup time, 0.5 ns hold time
+set_input_delay  -min  0.5 -clock [get_clocks clk_scan_in]  [get_ports {data_in}]
+set_input_delay  -max  0.5 -clock [get_clocks clk_scan_in]  [get_ports {data_in}]
 
-# Scan chain output 2.1 ns setup time, 0.1 ns hold time
-set_output_delay -min -0.1 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
-set_output_delay -max  2.1 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
+# Scan chain output 1.5 ns setup time, 1.5 ns hold time
+set_output_delay -min -1.5 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
+set_output_delay -max  1.5 -clock [get_clocks clk_scan_out] [get_ports {data_out}]
 
 # Misc
 set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]

template/scan_wrapper.v

@@ -45,9 +45,16 @@ module scan_wrapper_USER_MODULE_ID (
 
     // scan chain - link all the flops, with data coming from data_in
     assign scan_data_in = {scan_data_out[NUM_IOS-2:0], data_in};
-    
-    // end of the chain is the last scan flop's out
-    assign data_out = scan_data_out[NUM_IOS-1];
+
+    // end of the chain is a negedge FF to increase hold margin between blocks
+    sky130_fd_sc_hd__dfrtn_1 out_flop (
+        .RESET_B    (1'b1),
+        .CLK_N      (clk),
+        .D          (scan_data_out[NUM_IOS-1]),
+        .Q          (data_out),
+        .VPWR       (1'b1),
+        .VGND       (1'b0)
+    );
 
     // scan flops have a mux on their inputs to choose either data from the user module or the previous flop's output
     // https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_ls/cells/sdfxtp/README.html