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Pull requests: m-labs/misoc
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duc - Pipeline PhasedAccu for n>8 and allow non-log(2) values of n when n>8 (with improvements)
#172
opened Jul 22, 2025 by
Spaqin
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updated Aug 14, 2025
duc - Pipeline PhasedAccu for n>8 and allow non-log(2) values of n when n>8
#170
opened Jul 16, 2025 by
JILAelec
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updated Jul 24, 2025
Added support for Digilent Genesys 2 target
#130
opened Sep 1, 2022 by
kaolpr
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updated Mar 30, 2023
spi2: allow optional CS pin in SPIInterface
#109
opened Jun 22, 2021 by
drewrisinger
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updated Jun 22, 2021
1 task done
Proposal for Some Quality of Life Improvements
#107
opened Feb 5, 2021 by
HarryMakes
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Draft
updated Feb 5, 2021
csr: Proposal to accept CSRs with the same name owned by different submodules
#103
opened Oct 30, 2020 by
HarryMakes
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updated Nov 3, 2020
soc_core:allocate correct size for ROM.
#97
opened Jan 30, 2019 by
keesj
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updated Feb 6, 2019
added spi 1-bit mode, code from litex
#88
opened Jul 29, 2018 by
danielkucera
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updated Oct 11, 2018
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