PicoRV32 - A Size-Optimized RISC-V CPU

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

RTL, Cmodel, and testbench for NVDLA

Open source FPGA-based NIC and platform for in-network compute

SERV - The SErial RISC-V CPU

A small, light weight, RISC CPU soft core

Verilog library for ASIC and FPGA designers

Verilog PCI express components

An open source GPU based off of the AMD Southern Islands ISA.

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

32-bit Superscalar RISC-V CPU

An Open-source FPGA IP Generator

Various HDL (Verilog) IP Cores

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

RISC-V Formal Verification Framework

A High-performance Timing Analysis Tool for VLSI Systems

An open source library for image processing on FPGA.

synthesiseable ieee 754 floating point library in verilog

Bus bridges and other odds and ends

xkISP：Xinkai ISP IP Core (HLS)

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

A full-speed device-side USB peripheral core written in Verilog.

Open source design files for the TinyFPGA B-Series boards.

A 32-bit Microcontroller featuring a RISC-V core

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Betrusted main SoC design

FPGA implementation of Cellular Neural Network (CNN)