From 7e76fe2910765d2e5d8bf2a75d1b954fff06dfbb Mon Sep 17 00:00:00 2001
From: Robert Schilling <rschilling@rivosinc.com>
Date: Tue, 8 Oct 2024 20:22:33 +0200
Subject: [PATCH] [topgen] Make toplevel SV and chiplevel templates
 top-sepcific

This PR makes the toplevel verilog and chiplevel template top-specific
to better scale with multiple tops. This avoids adding multiple cases
to the template dealing with top-specic funcitonality.

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
---
 .../top_earlgrey}/templates/chiplevel.sv.tpl             | 0
 .../topgen => hw/top_earlgrey}/templates/toplevel.sv.tpl | 0
 hw/top_englishbreakfast/templates/chiplevel.sv.tpl       | 1 +
 hw/top_englishbreakfast/templates/toplevel.sv.tpl        | 1 +
 util/topgen.py                                           | 9 ++++++---
 5 files changed, 8 insertions(+), 3 deletions(-)
 rename {util/topgen => hw/top_earlgrey}/templates/chiplevel.sv.tpl (100%)
 rename {util/topgen => hw/top_earlgrey}/templates/toplevel.sv.tpl (100%)
 create mode 120000 hw/top_englishbreakfast/templates/chiplevel.sv.tpl
 create mode 120000 hw/top_englishbreakfast/templates/toplevel.sv.tpl

diff --git a/util/topgen/templates/chiplevel.sv.tpl b/hw/top_earlgrey/templates/chiplevel.sv.tpl
similarity index 100%
rename from util/topgen/templates/chiplevel.sv.tpl
rename to hw/top_earlgrey/templates/chiplevel.sv.tpl
diff --git a/util/topgen/templates/toplevel.sv.tpl b/hw/top_earlgrey/templates/toplevel.sv.tpl
similarity index 100%
rename from util/topgen/templates/toplevel.sv.tpl
rename to hw/top_earlgrey/templates/toplevel.sv.tpl
diff --git a/hw/top_englishbreakfast/templates/chiplevel.sv.tpl b/hw/top_englishbreakfast/templates/chiplevel.sv.tpl
new file mode 120000
index 0000000000000..30c0874b868f4
--- /dev/null
+++ b/hw/top_englishbreakfast/templates/chiplevel.sv.tpl
@@ -0,0 +1 @@
+../../top_earlgrey/templates/chiplevel.sv.tpl
\ No newline at end of file
diff --git a/hw/top_englishbreakfast/templates/toplevel.sv.tpl b/hw/top_englishbreakfast/templates/toplevel.sv.tpl
new file mode 120000
index 0000000000000..97c46850b164b
--- /dev/null
+++ b/hw/top_englishbreakfast/templates/toplevel.sv.tpl
@@ -0,0 +1 @@
+../../top_earlgrey/templates/toplevel.sv.tpl
\ No newline at end of file
diff --git a/util/topgen.py b/util/topgen.py
index 51c52eb4ed2cb..268be51112e9a 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -14,7 +14,7 @@
 from io import StringIO
 from itertools import chain
 from pathlib import Path
-from typing import Dict, List, Optional, Tuple
+from typing import Dict, List
 
 import hjson
 import tlgen
@@ -1214,16 +1214,19 @@ def render_template(template_path: str, rendered_path: Path,
 //                {seed}
 """.format(top_name=top_name, seed=completecfg["rnd_cnst_seed"])
 
+        # Top and chiplevel templates are top-specific
+        top_template_path = SRCTREE_TOP / "hw" / top_name / "templates"
+
         # SystemVerilog Top:
         # "toplevel.sv.tpl" -> "rtl/autogen/{top_name}.sv"
-        render_template(TOPGEN_TEMPLATE_PATH / "toplevel.sv.tpl",
+        render_template(top_template_path / "toplevel.sv.tpl",
                         out_path / "rtl" / "autogen" / f"{top_name}.sv",
                         gencmd=gencmd)
 
         # Multiple chip-levels (ASIC, FPGA, Verilator, etc)
         for target in topcfg["targets"]:
             target_name = target["name"]
-            render_template(TOPGEN_TEMPLATE_PATH / "chiplevel.sv.tpl",
+            render_template(top_template_path / "chiplevel.sv.tpl",
                             out_path /
                             f"rtl/autogen/chip_{topname}_{target_name}.sv",
                             gencmd=gencmd,