[rtl, syn] Fix typos

elliotb-lowrisc · elliotb-lowrisc · commit bd2599387f69 · 2025-06-27T11:09:24.000Z
diff --git a/rtl/ibex_alu.sv b/rtl/ibex_alu.sv
@@ -203,7 +203,7 @@ module ibex_alu #(
   //
   // Funnel Shifts
   // -------------
-  // For funnel shifs, operand_a_i is tied to rs1 in the first cycle and rs3 in the
+  // For funnel shifts, operand_a_i is tied to rs1 in the first cycle and rs3 in the
   // second cycle. operand_b_i is always tied to rs2. The order of applying the shift amount or
   // its complement is determined by bit [5] of shift_amt.
   //
@@ -484,7 +484,7 @@ module ibex_alu #(
     // butterfly network control signals. The adders in the intermediate value adder tree thus need
     // not be full 5-bit adders. We leave the optimization to the synthesis tools.
     //
-    // Consider the following 8-bit example for illustraton.
+    // Consider the following 8-bit example for illustration.
     //
     // let bitcnt_bits = 8'babcdefgh.
     //
@@ -783,7 +783,7 @@ module ibex_alu #(
           end
 
           ALU_XPERM_B: begin
-            // Convert byte to nibble indicies.
+            // Convert byte to nibble indices.
             for (int b = 0; b < 4; b++) begin
               sel[b*2 +  0] =   {sel_b[b], 1'b0};
               sel[b*2 +  1] =   {sel_b[b], 1'b1};
@@ -863,7 +863,7 @@ module ibex_alu #(
       // where P denotes lower 32 bits of the corresponding CRC polynomial, rev(a) the bit reversal
       // of a, n = 8,16, or 32 for .b, .h, .w -variants. {a, b} denotes bit concatenation.
       //
-      // Using barret reduction, one can show that
+      // Using Barrett reduction, one can show that
       //
       // M(x) mod P(x) = R(x) =
       //          (M(x) * x**n) & {deg(P(x)'{1'b1}}) ^ (M(x) x**-(deg(P(x) - n)) cx mu(x) cx P(x),
diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv
@@ -47,7 +47,7 @@ module ibex_controller #(
   input  logic                  instr_exec_i,            // Execution control, when clear ID/EX
                                                          // stage stops accepting instructions from
                                                          // IF
-  // to prefetcher
+  // to prefetch
   output logic                  instr_req_o,             // start fetching instructions
   output logic                  pc_set_o,                // jump to address set by pc_mux
   output ibex_pkg::pc_sel_e     pc_mux_o,                // IF stage fetch address selector
@@ -76,7 +76,7 @@ module ibex_controller #(
   input  logic                  irq_pending_i,           // interrupt request pending
   input  ibex_pkg::irqs_t       irqs_i,                  // interrupt requests qualified with
                                                          // mie CSR
-  input  logic                  irq_nm_ext_i,            // non-maskeable interrupt
+  input  logic                  irq_nm_ext_i,            // non-maskable interrupt
   output logic                  nmi_mode_o,              // core executing NMI handler
 
   // debug signals
@@ -248,7 +248,7 @@ module ibex_controller #(
 
       // Note that with the writeback stage store/load errors occur on the instruction in writeback,
       // all other exception/faults occur on the instruction in ID/EX. The faults from writeback
-      // must take priority as that instruction is architecurally ordered before the one in ID/EX.
+      // must take priority as that instruction is architecturally ordered before the one in ID/EX.
       if (store_err_q) begin
         store_err_prio = 1'b1;
       end else if (load_err_q) begin
@@ -317,7 +317,7 @@ module ibex_controller #(
 
     assign entering_nmi = nmi_mode_d & ~nmi_mode_q;
 
-    // Load integerity error internal interrupt
+    // Load integrity error internal interrupt
     always_comb begin
       mem_resp_intg_err_addr_d        = mem_resp_intg_err_addr_q;
       mem_resp_intg_err_irq_set       = 1'b0;
@@ -428,7 +428,7 @@ module ibex_controller #(
 
   // Record the debug cause outside of the FSM
   // The decision to enter debug_mode and the write of the cause to DCSR happen
-  // in seperate steps within the FSM. Hence, there are a small number of cycles
+  // in separate steps within the FSM. Hence, there are a small number of cycles
   // where a change in external stimulus can cause the cause to be recorded incorrectly.
   assign debug_cause_d = trigger_match_i                    ? DBG_CAUSE_TRIGGER :
                          ebrk_insn_prio & ebreak_into_debug ? DBG_CAUSE_EBREAK  :
@@ -935,7 +935,7 @@ module ibex_controller #(
     debug_mode_d != debug_mode_q |-> flush_id_o & pc_set_o)
 
   `ifdef RVFI
-    // Workaround for internal verilator error when using hierarchical refers to calcuate this
+    // Workaround for internal verilator error when using hierarchical refers to calculate this
     // directly in ibex_core
     logic rvfi_flush_next;
 
diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
@@ -109,7 +109,7 @@ module ibex_core import ibex_pkg::*; #(
   input  logic                         irq_timer_i,
   input  logic                         irq_external_i,
   input  logic [14:0]                  irq_fast_i,
-  input  logic                         irq_nm_i,       // non-maskeable interrupt
+  input  logic                         irq_nm_i,       // non-maskable interrupt
   output logic                         irq_pending_o,
 
   // Debug Interface
@@ -291,7 +291,7 @@ module ibex_core import ibex_pkg::*; #(
   logic [31:0] csr_rdata;
   logic [31:0] csr_wdata;
   logic        illegal_csr_insn_id;    // CSR access to non-existent register,
-                                       // with wrong priviledge level,
+                                       // with wrong privilege level,
                                        // or missing write permissions
 
   // Data Memory Control
@@ -897,7 +897,7 @@ module ibex_core import ibex_pkg::*; #(
     logic [1:0] rf_ecc_err_a, rf_ecc_err_b;
     logic       rf_ecc_err_a_id, rf_ecc_err_b_id;
 
-    // ECC checkbit generation for regiter file wdata
+    // ECC checkbit generation for register file wdata
     prim_secded_inv_39_32_enc regfile_ecc_enc (
       .data_i(rf_wdata_wb),
       .data_o(rf_wdata_wb_ecc_o)
@@ -1537,7 +1537,7 @@ module ibex_core import ibex_pkg::*; #(
 
 
   // rvfi_irq_valid signals an interrupt event to the cosim. These should only occur when the RVFI
-  // pipe is empty so just send it straigh through.
+  // pipe is empty so just send it straight through.
   for (genvar i = 0; i < RVFI_STAGES + 1; i = i + 1) begin : g_rvfi_irq_valid
     if (i == 0) begin : g_rvfi_irq_valid_first_stage
       always_ff @(posedge clk_i or negedge rst_ni) begin
diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv
@@ -109,7 +109,7 @@ module ibex_cs_registers #(
   input  ibex_pkg::exc_cause_t csr_mcause_i,
   input  logic [31:0]          csr_mtval_i,
   output logic                 illegal_csr_insn_o,     // access to non-existent CSR,
-                                                        // with wrong priviledge level, or
+                                                        // with wrong privilege level, or
                                                         // missing write permissions
   output logic                 double_fault_seen_o,
   // Performance Counters
@@ -199,7 +199,7 @@ module ibex_cs_registers #(
   } dcsr_t;
 
   // Partial CPU control and status register fields
-  // ICache scramble key valid (ic_scr_key_valid) is registered seperately to this struct. This is
+  // ICache scramble key valid (ic_scr_key_valid) is registered separately to this struct. This is
   // because it is sampled from the top-level every cycle whilst the other fields only change
   // occasionally.
   typedef struct packed {
@@ -343,7 +343,7 @@ module ibex_cs_registers #(
       CSR_MIMPID: csr_rdata_int = CsrMimpId;
       // mhartid: unique hardware thread id
       CSR_MHARTID: csr_rdata_int = hart_id_i;
-      // mconfigptr: pointer to configuration data structre
+      // mconfigptr: pointer to configuration data structure
       CSR_MCONFIGPTR: csr_rdata_int = CSR_MCONFIGPTR_VALUE;
 
       // mstatus: always M-mode, contains IE bit
diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv
@@ -1196,7 +1196,7 @@ module ibex_decoder #(
   // instruction exceptions
   assign illegal_insn_o = illegal_insn | illegal_reg_rv32e;
 
-  // do not propgate regfile write enable if non-available registers are accessed in RV32E
+  // do not propagate regfile write enable if non-available registers are accessed in RV32E
   assign rf_we_o = rf_we & ~illegal_reg_rv32e;
 
   // Not all bits are used
diff --git a/rtl/ibex_dummy_instr.sv b/rtl/ibex_dummy_instr.sv
@@ -96,9 +96,9 @@ module ibex_dummy_instr import ibex_pkg::*; #(
   // LFSR with a mask applied (based on CSR config data) to shorten the period if required.
   assign dummy_cnt_threshold = lfsr_data.cnt & {dummy_instr_mask_i,{TIMEOUT_CNT_W-3{1'b1}}};
   assign dummy_cnt_incr      = dummy_cnt_q + {{TIMEOUT_CNT_W-1{1'b0}},1'b1};
-  // Clear the counter everytime a new instruction is inserted
+  // Clear the counter every time a new instruction is inserted
   assign dummy_cnt_d         = insert_dummy_instr ? '0 : dummy_cnt_incr;
-  // Increment the counter for each executed instruction while dummy instuctions are
+  // Increment the counter for each executed instruction while dummy instructions are
   // enabled.
   assign dummy_cnt_en        = dummy_instr_en_i & id_in_ready_i &
                                (fetch_valid_i | insert_dummy_instr);
diff --git a/rtl/ibex_ex_block.sv b/rtl/ibex_ex_block.sv
@@ -23,7 +23,7 @@ module ibex_ex_block #(
   input  logic                  alu_instr_first_cycle_i,
 
   // Branch Target ALU
-  // All of these signals are unusued when BranchTargetALU == 0
+  // All of these signals are unused when BranchTargetALU == 0
   input  logic [31:0]           bt_a_operand_i,
   input  logic [31:0]           bt_b_operand_i,
 
@@ -197,7 +197,7 @@ module ibex_ex_block #(
   assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we);
 
 `ifdef INC_ASSERT
-  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // This is intended to be accessed via hierarchical references so isn't output from this module nor
   // used in any logic in this module
   logic sva_multdiv_fsm_idle;
 
diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv
@@ -76,7 +76,7 @@ module ibex_icache import ibex_pkg::*; #(
   logic [ADDR_W-1:0]                      lookup_addr_aligned;
   logic [ADDR_W-1:0]                      prefetch_addr_d, prefetch_addr_q;
   logic                                   prefetch_addr_en;
-  // Cache pipelipe IC0 signals
+  // Cache pipeline IC0 signals
   logic                                   lookup_throttle;
   logic                                   lookup_req_ic0;
   logic [ADDR_W-1:0]                      lookup_addr_ic0;
@@ -98,7 +98,7 @@ module ibex_icache import ibex_pkg::*; #(
   logic [IC_NUM_WAYS-1:0]                 data_banks_ic0;
   logic                                   data_write_ic0;
   logic [LineSizeECC-1:0]                 data_wdata_ic0;
-  // Cache pipelipe IC1 signals
+  // Cache pipeline IC1 signals
   logic [TagSizeECC-1:0]                  tag_rdata_ic1  [IC_NUM_WAYS];
   logic [LineSizeECC-1:0]                 data_rdata_ic1 [IC_NUM_WAYS];
   logic [LineSizeECC-1:0]                 hit_data_ecc_ic1;
@@ -1112,7 +1112,7 @@ module ibex_icache import ibex_pkg::*; #(
         inval_index_en  = 1'b1;
 
         if (icache_inval_i) begin
-          // If a new invalidaiton requests comes in go back to the beginning with a new scramble
+          // If a new invalidation requests comes in go back to the beginning with a new scramble
           // key
           ic_scr_key_req_o = 1'b1;
           inval_state_d = AWAIT_SCRAMBLE_KEY;
@@ -1127,7 +1127,7 @@ module ibex_icache import ibex_pkg::*; #(
           ic_scr_key_req_o = 1'b1;
           inval_state_d = AWAIT_SCRAMBLE_KEY;
         end else begin
-          // Allow other cache activies whilst in IDLE and no invalidation has been requested
+          // Allow other cache activities whilst in IDLE and no invalidation has been requested
           inval_block_cache = 1'b0;
         end
       end
diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv
@@ -519,7 +519,7 @@ module ibex_id_stage #(
   // instructions are in general rare and not part of performance critical parts of the code.
   //
   // No flush is triggered for a small number of specific CSRs. These are ones that have been
-  // specifically identified to be a) likely to be modifed in exception handlers and b) safe to
+  // specifically identified to be a) likely to be modified in exception handlers and b) safe to
   // alter without a flush.
   assign no_flush_csr_addr = csr_addr_o inside {CSR_MSCRATCH, CSR_MEPC};
 
@@ -578,7 +578,7 @@ module ibex_id_stage #(
     .controller_run_o   (controller_run),
     .instr_exec_i       (instr_exec_i),
 
-    // to prefetcher
+    // to prefetch
     .instr_req_o           (instr_req_o),
     .pc_set_o              (pc_set_o),
     .pc_mux_o              (pc_mux_o),
@@ -972,7 +972,7 @@ module ibex_id_stage #(
                        (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i));
 
     // If we stall a load in ID for any reason, it must not make an LSU request
-    // (otherwide we might issue two requests for the same instruction)
+    // (otherwise we might issue two requests for the same instruction)
     `ASSERT(IbexStallMemNoRequest,
       instr_valid_i & lsu_req_dec & ~instr_done |-> ~lsu_req_done_i)
 
@@ -1040,7 +1040,7 @@ module ibex_id_stage #(
     assign rf_rd_b_wb_match_o = 1'b0;
 
     // First cycle of a load or store is always the request. We're expecting a response the cycles
-    // following. Note if the request isn't immediatly accepted these signals will still assert.
+    // following. Note if the request isn't immediately accepted these signals will still assert.
     // However in this case the LSU won't signal a response as it's still waiting for the grant
     // (even if the external memory bus signals are glitched to generate a false response).
     assign expecting_load_resp_o  = instr_valid_i & lsu_req_dec & ~instr_first_cycle & ~lsu_we;
@@ -1146,7 +1146,7 @@ module ibex_id_stage #(
   `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i)
 
   // Check that when ID stage is ready for next instruction FSM is in FIRST_CYCLE state the
-  // following cycle (when the new instructon may begin executing).
+  // following cycle (when the new instruction may begin executing).
   `ASSERT(IbexMoveToFirstCycleWhenIdReady, id_in_ready_o |=> id_fsm_q == FIRST_CYCLE)
 
   `ifdef CHECK_MISALIGNED
diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv
@@ -541,7 +541,8 @@ module ibex_if_stage import ibex_pkg::*; #(
     logic        prev_instr_seq_q, prev_instr_seq_d;
 
     // Do not check for sequential increase after a branch, jump, exception, interrupt or debug
-    // request, all of which will set branch_req. Also do not check after reset or for dummys.
+    // request, all of which will set branch_req. Also do not check after reset or for dummy
+    // instructions.
     assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) &
         ~branch_req & ~if_instr_err & ~stall_dummy_instr;
 
diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv
@@ -565,7 +565,7 @@ module ibex_load_store_unit #(
   // fcov_mis_rvalid_2: Set when response is received for the second half
   logic fcov_mis_rvalid_1, fcov_mis_rvalid_2;
 
-  // Set when the first half of a misaligned access saw a bus errror
+  // Set when the first half of a misaligned access saw a bus error
   logic fcov_mis_bus_err_1_d, fcov_mis_bus_err_1_q;
 
   assign fcov_mis_rvalid_1 = ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_RVALID_MIS_GNTS_DONE} &&
diff --git a/rtl/ibex_multdiv_fast.sv b/rtl/ibex_multdiv_fast.sv
@@ -254,7 +254,7 @@ module ibex_multdiv_fast #(
 
     assign unused_mult1_res_uns = mult1_res_uns[33:32];
 
-    // States must be knwon/valid.
+    // States must be known/valid.
     `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
 
     assign sva_mul_fsm_idle = mult_state_q == MULL;
@@ -374,7 +374,7 @@ module ibex_multdiv_fast #(
       end
     end
 
-    // States must be knwon/valid.
+    // States must be known/valid.
     `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q)
 
     assign sva_mul_fsm_idle = mult_state_q == ALBL;
@@ -528,15 +528,15 @@ module ibex_multdiv_fast #(
 
   assign valid_o = mult_valid | div_valid;
 
-  // States must be knwon/valid.
+  // States must be known/valid.
   `ASSERT(IbexMultDivStateValid, md_state_q inside {
       MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH})
 
 `ifdef INC_ASSERT
   logic sva_fsm_idle;
   logic unused_sva_fsm_idle;
 
-  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // This is intended to be accessed via hierarchical references so isn't output from this module nor
   // used in any logic in this module
   assign sva_fsm_idle = (md_state_q == MD_IDLE) && sva_mul_fsm_idle;
   // Mark the sva_fsm_idle as unused to avoid lint issues
diff --git a/rtl/ibex_multdiv_slow.sv b/rtl/ibex_multdiv_slow.sv
@@ -374,7 +374,7 @@ module ibex_multdiv_slow
   logic sva_fsm_idle;
   logic unused_sva_fsm_idle;
 
-  // This is intended to be accessed via hierarchal references so isn't output from this module nor
+  // This is intended to be accessed via hierarchical references so isn't output from this module nor
   // used in any logic in this module
   assign sva_fsm_idle = (md_state_q == MD_IDLE);
   // Mark the sva_fsm_idle as unused to avoid lint issues
diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv
@@ -388,7 +388,7 @@ package ibex_pkg;
   parameter int unsigned PMP_MAX_REGIONS      = 16;
   parameter int unsigned PMP_CFG_W            = 8;
 
-  // PMP acces type
+  // PMP access type
   parameter int unsigned PMP_I  = 0;
   parameter int unsigned PMP_I2 = 1;
   parameter int unsigned PMP_D  = 2;
@@ -624,7 +624,7 @@ package ibex_pkg;
   localparam logic [31:0] CSR_MARCHID_VALUE = {1'b0, 31'd22};
 
   // Machine Configuration Pointer
-  // 0 indicates the configuration data structure does not eixst. Ibex implementors may wish to
+  // 0 indicates the configuration data structure does not exist. Ibex implementers may wish to
   // alter this to point to their system specific configuration data structure.
   localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0;
 
@@ -642,7 +642,7 @@ package ibex_pkg;
   parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonceDefault =
       64'hf79780bc735f3843;
 
-  // Mult-bit signal used for security hardening. For non-secure implementation all bits other than
+  // Multi-bit signal used for security hardening. For non-secure implementation all bits other than
   // the bottom bit are ignored.
   parameter int IbexMuBiWidth = 4;
   typedef logic [IbexMuBiWidth-1:0] ibex_mubi_t;
@@ -680,7 +680,7 @@ package ibex_pkg;
     '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0}  // region 15
   };
 
-  // Addresses are given in byte granularity for readibility. A minimum of two
+  // Addresses are given in byte granularity for readability. A minimum of two
   // bits will be stripped off the bottom (PMPGranularity == 0) with more stripped
   // off at coarser granularities.
   parameter logic [33:0] PmpAddrRst[16] = '{
diff --git a/rtl/ibex_prefetch_buffer.sv b/rtl/ibex_prefetch_buffer.sv
@@ -4,7 +4,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 /**
- * Prefetcher Buffer for 32 bit memory interface
+ * Prefetch Buffer for 32 bit memory interface
  *
  * Prefetch Buffer that caches instructions. This cuts overly long critical
  * paths to the instruction cache.
@@ -134,7 +134,7 @@ module ibex_prefetch_buffer #(
   // 2. fetch_addr_q  - This is our next address to fetch from. It is updated on branches to
   //                    capture the new address, and then for each new request issued.
   // A third address is tracked in the fetch FIFO itself:
-  // 3. instr_addr_q  - This is the address at the head of the FIFO, efectively our oldest fetched
+  // 3. instr_addr_q  - This is the address at the head of the FIFO, effectively our oldest fetched
   //                    address. This address is updated on branches, and does its own increment
   //                    each time the FIFO is popped.
 
diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv
diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv
diff --git a/shared/rtl/bus.sv b/shared/rtl/bus.sv
diff --git a/shared/rtl/sim/simulator_ctrl.sv b/shared/rtl/sim/simulator_ctrl.sv
diff --git a/syn/README.md b/syn/README.md
diff --git a/syn/python/get_kge.py b/syn/python/get_kge.py
diff --git a/syn/tcl/lr_synth_flow_var_setup.tcl b/syn/tcl/lr_synth_flow_var_setup.tcl
