Add support for the PYNQ-Z2 board

nuntipat · nuntipat · commit 0689f3733175 · 2023-06-06T16:17:54.000-04:00
diff --git a/README.md b/README.md
@@ -466,6 +466,17 @@ repository root:
 fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system
 ```
 
+To build for other support development boards such as the NewAE CW305, NewAE CW312-A35, or the TUL PYNQ-Z2, use the command
+
+```
+# NewAE CW305
+fusesoc --cores-root=. run --target=synth_cw305 --setup --build lowrisc:ibex:demo_system
+# NewAE CW312-A35
+fusesoc --cores-root=. run --target=synth_cw312a35 --setup --build lowrisc:ibex:demo_system
+# TUL PYNQ-Z2
+fusesoc --cores-root=. run --target=synth_pynqz2 --setup --build lowrisc:ibex:demo_system
+```
+
 ## Programming FPGA
 
 To program the FPGA, either use FuseSoC again
@@ -504,6 +515,14 @@ In this case, you may try using `sudo`.
 
 To exit from the `screen` command, you should press control and a together, then release these two keys and press d.
 
+### Note on UART connection for the PYNQ-Z2 development board
+
+There is no direct connection between the FTDI chip and the programming logic (PL) side of the Zynq 7020 SOC used in the PYNQ-Z2 development board. However, we may attach a 2.54mm pin header to J13 (pin 1: UART RX, pin 2: UART TX) on the board, route the UART signals to any available I/O pins, and make a connection using jumper wires.
+
+The following image shows a one-way connection between the TX pin of the Ibex and the RX pin of the FTDI chip.
+
+![PYNQ-Z2 UART jumper wire connection](doc/PynqZ2UARTConnection.jpg)
+
 ## Debugging an application
 
 Either load an application and halt (see above) or start a new OpenOCD instance
diff --git a/data/pins_pynqz2.xdc b/data/pins_pynqz2.xdc
diff --git a/doc/PynqZ2UARTConnection.jpg b/doc/PynqZ2UARTConnection.jpg
diff --git a/ibex_demo_system.core b/ibex_demo_system.core
@@ -33,6 +33,15 @@ filesets:
       - rtl/fpga/top_cw312a35.sv
     file_type: systemVerilogSource
 
+  files_xilinx_pynqz2:
+    depend:
+      - lowrisc:ibex:rv_timer
+      - lowrisc:ibex:fpga_xilinx_shared
+    files:
+      - rtl/fpga/top_pynqz2.sv
+      - rtl/fpga/clkgen_pynqz2.sv
+    file_type: systemVerilogSource
+
   files_verilator:
     depend:
       - lowrisc:ibex:sim_shared
@@ -60,6 +69,10 @@ filesets:
       - data/pins_cw312a35.xdc
     file_type: xdc
 
+  files_constraints_pynqz2:
+    files:
+      - data/pins_pynqz2.xdc
+    file_type: xdc
 
 
 parameters:
@@ -125,6 +138,19 @@ targets:
     parameters:
       - SRAMInitFile
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
+  synth_pynqz2:
+    <<: *default_target
+    default_tool: vivado
+    filesets_append:
+      - files_xilinx_pynqz2
+      - files_constraints_pynqz2
+    toplevel: top_pynqz2
+    tools:
+      vivado:
+        part: "xc7z020clg400-1"
+    parameters:
+      - SRAMInitFile
+      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
 
   sim:
     <<: *default_target
diff --git a/rtl/fpga/clkgen_pynqz2.sv b/rtl/fpga/clkgen_pynqz2.sv
@@ -0,0 +1,80 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module clkgen_pynqz2 (
+    input IO_CLK,
+    input IO_RST_N,
+    output clk_sys,
+    output rst_sys_n
+);
+  logic locked_pll;
+  logic io_clk_buf;
+  logic clk_50_buf;
+  logic clk_50_unbuf;
+  logic clk_fb_buf;
+  logic clk_fb_unbuf;
+
+  // input buffer
+  IBUF io_clk_ibuf(
+    .I (IO_CLK),
+    .O (io_clk_buf)
+  );
+
+  PLLE2_ADV #(
+    .BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("ZHOLD"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (5),
+    .CLKFBOUT_MULT        (34),
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (17),
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (8.000)
+  ) pll (
+    .CLKFBOUT            (clk_fb_unbuf),
+    .CLKOUT0             (clk_50_unbuf),
+    .CLKOUT1             (),
+    .CLKOUT2             (),
+    .CLKOUT3             (),
+    .CLKOUT4             (),
+    .CLKOUT5             (),
+     // Input clock control
+    .CLKFBIN             (clk_fb_buf),
+    .CLKIN1              (io_clk_buf),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
+    .CLKINSEL            (1'b1),
+    // Ports for dynamic reconfiguration
+    .DADDR               (7'h0),
+    .DCLK                (1'b0),
+    .DEN                 (1'b0),
+    .DI                  (16'h0),
+    .DO                  (),
+    .DRDY                (),
+    .DWE                 (1'b0),
+    // Other control and status signals
+    .LOCKED              (locked_pll),
+    .PWRDWN              (1'b0),
+    // Do not reset PLL on external reset, otherwise ILA disconnects at a reset
+    .RST                 (1'b0));
+
+  // output buffering
+  BUFG clk_fb_bufg (
+    .I (clk_fb_unbuf),
+    .O (clk_fb_buf)
+  );
+
+  BUFG clk_50_bufg (
+    .I (clk_50_unbuf),
+    .O (clk_50_buf)
+  );
+
+  // outputs
+  // clock
+  assign clk_sys = clk_50_buf;
+
+  // reset
+  assign rst_sys_n = locked_pll & IO_RST_N;
+endmodule
diff --git a/rtl/fpga/top_pynqz2.sv b/rtl/fpga/top_pynqz2.sv
@@ -0,0 +1,59 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
+module top_pynqz2 (
+  // These inputs are defined in data/pins_pynqz2.xdc
+  input               IO_CLK,
+  input               IO_RST,
+  input  [1:0]        SW,
+  input  [2:0]        BTN,
+  output [3:0]        LED,
+  output [3:0]        GPIOS,
+  output [5:0]        RGB_LED,
+  input               UART_RX,
+  output              UART_TX,
+  input               SPI_RX,
+  output              SPI_TX,
+  output              SPI_SCK
+);
+  parameter SRAMInitFile = "";
+
+  logic clk_sys, rst_sys_n;
+
+  // Instantiating the Ibex Demo System.
+  ibex_demo_system #(
+    .GpiWidth(5),
+    .GpoWidth(8),
+    .PwmWidth(6),
+    .SRAMInitFile(SRAMInitFile)
+  ) u_ibex_demo_system (
+    //input
+    .clk_sys_i(clk_sys),
+    .rst_sys_ni(rst_sys_n),
+    .gp_i({SW, BTN}),
+    .uart_rx_i(UART_RX),
+
+    //output
+    .gp_o({LED, GPIOS}),
+    .pwm_o(RGB_LED),
+    .uart_tx_o(UART_TX),
+
+    .spi_rx_i(SPI_RX),
+    .spi_tx_o(SPI_TX),
+    .spi_sck_o(SPI_SCK)
+  );
+
+  logic IO_RST_N;
+  assign IO_RST_N = ~IO_RST;
+
+  // Generating the system clock and reset for the FPGA.
+  clkgen_pynqz2 clkgen(
+    .IO_CLK,
+    .IO_RST_N,
+    .clk_sys,
+    .rst_sys_n
+  );
+
+endmodule
diff --git a/util/load_demo_system.sh b/util/load_demo_system.sh
@@ -3,31 +3,42 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-if [ $# -ne 2 ]; then
-  echo "Usage $0 run|halt elf_file"
+if [ $# -ne 3 ]; then
+  echo "Usage $0 artya7|pynqz2 run|halt elf_file"
   exit 1
 fi
 
-if [ ! -f $2 ]; then
-  echo "$2 does not exist"
+if [ ! -f $3 ]; then
+  echo "$3 does not exist"
   exit 1
 fi
 
-if [ $1 != "halt" ] && [ $1 != "run" ]; then
-  echo "First argument must be halt or run"
+if [ $2 != "halt" ] && [ $2 != "run" ]; then
+  echo "Second argument must be halt or run"
+  exit 1
+fi
+
+if [ $1 != "artya7" ] && [ $1 != "pynqz2" ]; then
+  echo "First argument must be artya7 or pynqz2"
   exit 1
 fi
 
 EXIT_CMD=''
 
-if [ $1 = "run" ]; then
+if [ $2 = "run" ]; then
   EXIT_CMD='-c "exit"'
 fi
 
 SCRIPT_DIR="$(dirname "$(readlink -e "$0")")"
 
-openocd -f $SCRIPT_DIR/arty-a7-openocd-cfg.tcl -c "load_image $2 0x0" \
- -c "verify_image $2 0x0" \
+if [ $1 = "artya7" ]; then
+  SCRIPT_FILENAME="arty-a7-openocd-cfg.tcl"
+elif [ $1 = "pynqz2" ]; then
+  SCRIPT_FILENAME="pynq-z2-openocd-cfg.tcl"
+fi
+
+openocd -f $SCRIPT_DIR/$SCRIPT_FILENAME -c "load_image $3 0x0" \
+ -c "verify_image $3 0x0" \
  -c "echo \"Doing reset\"" \
- -c "reset $1" \
+ -c "reset $2" \
  $EXIT_CMD
diff --git a/util/pynq-z2-openocd-cfg.tcl b/util/pynq-z2-openocd-cfg.tcl
@@ -0,0 +1,43 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+adapter driver ftdi
+transport select jtag
+
+ftdi_device_desc "TUL"
+ftdi_vid_pid 0x0403 0x6010
+ftdi_channel 0
+ftdi_layout_init 0x0088 0x008b
+reset_config none
+
+# Configure JTAG chain and the target processor
+set _CHIPNAME riscv
+
+# Configure JTAG expected ID
+set _EXPECTED_ID 0x23727093
+
+jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_EXPECTED_ID -ignore-version
+
+# just to avoid a warning about the auto-detected arm core
+# see: https://github.com/pulp-platform/riscv-dbg/blob/master/doc/debug-system.md
+jtag newtap arm_unused tap -irlen 4 -expected-id 0x4ba00477
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_ir idcode 0x09
+riscv set_ir dtmcs 0x22
+riscv set_ir dmi 0x23
+
+adapter speed 10000
+
+riscv set_prefer_sba on
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+gdb_breakpoint_override hard
+
+reset_config none
+
+init
+halt
