Single-file double-precision SSE2 FFT routines

A recreated program for the ABC80 from 1981, and the context of its being

Red is a next-generation programming language strongly inspired by Rebol, but with a broader field of usage thanks to its native-code compiler, from system programming to high-level scripting and c…

The open-source pocket groovebox

Chisel library for Unum Type-III Posit Arithmetic

Async Web Server for ESP8266 and ESP32

A browser based code editor

Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.

k for BareMetal

A graphical processor simulator and assembly editor for the RISC-V ISA

Code for the "fake BIOS" RISC-V example

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

most primitive risc-v core ever written by me in VHDL. It implements only I instruction set.

RISC-V Instruction Set Manual

Examples for compiling code using the RISC-V gnu toolchain

RISC-V Assembler and Runtime Simulator

RARS -- RISC-V Assembler and Runtime Simulator

RISC-V instruction set simulator built for education

RISC-V instruction set simulator built for education

Standalone C compiler for RISC-V and ARM

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

A Fully functional RISC-V Proccessor written in SystemVerilog and tested using Verilator.

RISCV model for Verilator/FPGA targets

Verilog implementation of multi-stage 32-bit RISC-V processor

Learning FPGA, yosys, nextpnr, and RISC-V

PicoRV32 - A Size-Optimized RISC-V CPU

SERV - The SErial RISC-V CPU

32-bit Superscalar RISC-V CPU