[Exegesis][RISCV] Add RISCV support for llvm-exegesis #89047
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-tools-llvm-exegesis Author: None (AnastasiyaChernikova) ChangesLlvm-exegesis RISCV port is a result of team effort. Below everyone involved listed. Patch is 58.39 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/89047.diff 27 Files Affected:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 92f405b5f6acbf..9e83add7c4c3d9 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -299,6 +299,9 @@ enum OperandType : unsigned {
OPERAND_RVKRNUM_2_14,
OPERAND_SPIMM,
OPERAND_LAST_RISCV_IMM = OPERAND_SPIMM,
+ // Operand is a 3-bit rounding mode, '111' indicates FRM register.
+ // Represents 'frm' argument passing to floating-point operations.
+ OPERAND_FRMARG,
// Operand is either a register or uimm5, this is used by V extension pseudo
// instructions to represent a value that be passed as AVL to either vsetvli
// or vsetivli.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index f9dadc6c0d4895..dddbeeddffa5b4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -509,7 +509,7 @@ class BranchCC_rri<bits<3> funct3, string opcodestr>
let isTerminator = 1;
}
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0, UseNamedOperandTable = 1 in {
class Load_ri<bits<3> funct3, string opcodestr>
: RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
opcodestr, "$rd, ${imm12}(${rs1})">;
@@ -524,7 +524,7 @@ class HLoad_r<bits<7> funct7, bits<5> funct5, string opcodestr>
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1, UseNamedOperandTable = 1 in {
class Store_rri<bits<3> funct3, string opcodestr>
: RVInstS<funct3, OPC_STORE, (outs),
(ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 7d89608de1223f..846f90e83df809 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -130,6 +130,8 @@ def frmarg : Operand<XLenVT> {
let ParserMatchClass = FRMArg;
let PrintMethod = "printFRMArg";
let DecoderMethod = "decodeFRMArg";
+ let OperandType = "OPERAND_FRMARG";
+ let OperandNamespace = "RISCVOp";
}
// Variants of the rounding mode operand that default to 'rne'. This is used
@@ -150,6 +152,8 @@ def frmarglegacy : Operand<XLenVT> {
let ParserMatchClass = FRMArgLegacy;
let PrintMethod = "printFRMArgLegacy";
let DecoderMethod = "decodeFRMArg";
+ let OperandType = "OPERAND_FRMARG";
+ let OperandNamespace = "RISCVOp";
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
new file mode 100644
index 00000000000000..e07452814c9096
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
@@ -0,0 +1,59 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOAND_D -mattr="+a" |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'AMOAND_D [[RE01:X[0-9]+]] X10 [[RE01:X[0-9]+]]'
+TEST1-NEXT: config: ''
+TEST1-NEXT: register_initial_values:
+TEST1-NEXT: - '[[RE01:X[0-9]+]]=0x0'
+TEST1-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOADD_W -mattr="+a" |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'AMOADD_W [[RE02:X[0-9]+]] X10 [[RE02:X[0-9]+]]'
+TEST2-NEXT: config: ''
+TEST2-NEXT: register_initial_values:
+TEST2-NEXT: - '[[RE02:X[0-9]+]]=0x0'
+TEST2-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOMAXU_D -mattr="+a" |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'AMOMAXU_D [[RE03:X[0-9]+]] X10 [[RE03:X[0-9]+]]'
+TEST3-NEXT: config: ''
+TEST3-NEXT: register_initial_values:
+TEST3-NEXT: - '[[RE03:X[0-9]+]]=0x0'
+TEST3-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOMIN_W -mattr="+a" |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'AMOMIN_W [[RE04:X[0-9]+]] X10 [[RE04:X[0-9]+]]'
+TEST4-NEXT: config: ''
+TEST4-NEXT: register_initial_values:
+TEST4-NEXT: - '[[RE04:X[0-9]+]]=0x0'
+TEST4-LAST: ...
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=AMOXOR_D -mattr="+a" |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'AMOXOR_D [[RE05:X[0-9]+]] X10 [[RE05:X[0-9]+]]'
+TEST5-NEXT: config: ''
+TEST5-NEXT: register_initial_values:
+TEST5-NEXT: - '[[RE05:X[0-9]+]]=0x0'
+TEST5-LAST: ...
\ No newline at end of file
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
new file mode 100644
index 00000000000000..14a517750f3462
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
@@ -0,0 +1,65 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ADDI -mattr=+c |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'C_ADDI [[REG01:X[0-9]+]] [[RE02:X[0-9]+]] [[IMM0:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ADDIW -mattr=+c |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'C_ADDIW [[REG11:X[0-9]+]] [[RE12:X[0-9]+]] [[IMM1:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_ANDI -mattr=+c |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'C_ANDI [[REG31:X[0-9]+]] [[REG32:X[0-9]+]] [[IMM3:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SLLI -mattr=+c |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'C_SLLI [[REG81:X[0-9]+]] [[REG82:X[0-9]+]] [[IMM8:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SRAI -mattr=+c |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'C_SRAI [[REG91:X[0-9]+]] [[REG92:X[0-9]+]] [[IMM9:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_SRLI -mattr=+c |& FileCheck --check-prefix=TEST6 %s
+
+TEST6: ---
+TEST6-NEXT: mode: latency
+TEST6-NEXT: key:
+TEST6-NEXT: instructions:
+TEST6-NEXT: - 'C_SRLI [[REG101:X[0-9]+]] [[REG102:X[0-9]+]] [[IMM10:i_0x[0-9]+]]'
+TEST6-LAST: ...
+
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_LD -mattr=+c |& FileCheck --check-prefix=TEST7 %s
+
+TEST7: ---
+TEST7-NEXT: mode: latency
+TEST7-NEXT: key:
+TEST7-NEXT: instructions:
+TEST7-NEXT: - 'C_LD [[REG61:X[0-9]+]] [[REG62:X[0-9]+]] [[IMM6:i_0x[0-9]+]]'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=C_LW -mattr=+c |& FileCheck --check-prefix=TEST8 %s
+
+TEST8: ---
+TEST8-NEXT: mode: latency
+TEST8-NEXT: key:
+TEST8-NEXT: instructions:
+TEST8-NEXT: - 'C_LW [[REG71:X[0-9]+]] [[REG72:X[0-9]+]] [[IMM7:i_0x[0-9]+]]'
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
new file mode 100644
index 00000000000000..74ee7580c6054c
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-load.s
@@ -0,0 +1,60 @@
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LD |& FileCheck --check-prefix=TEST1 %s
+
+TEST1: ---
+TEST1-NEXT: mode: latency
+TEST1-NEXT: key:
+TEST1-NEXT: instructions:
+TEST1-NEXT: - 'LD X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LW |& FileCheck --check-prefix=TEST2 %s
+
+TEST2: ---
+TEST2-NEXT: mode: latency
+TEST2-NEXT: key:
+TEST2-NEXT: instructions:
+TEST2-NEXT: - 'LW X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LH |& FileCheck --check-prefix=TEST3 %s
+
+TEST3: ---
+TEST3-NEXT: mode: latency
+TEST3-NEXT: key:
+TEST3-NEXT: instructions:
+TEST3-NEXT: - 'LH X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LWU |& FileCheck --check-prefix=TEST4 %s
+
+TEST4: ---
+TEST4-NEXT: mode: latency
+TEST4-NEXT: key:
+TEST4-NEXT: instructions:
+TEST4-NEXT: - 'LWU X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LBU |& FileCheck --check-prefix=TEST5 %s
+
+TEST5: ---
+TEST5-NEXT: mode: latency
+TEST5-NEXT: key:
+TEST5-NEXT: instructions:
+TEST5-NEXT: - 'LBU X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LUI |& FileCheck --check-prefix=TEST6 %s
+
+TEST6: LUI: No strategy found to make the execution serial
+
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LB |& FileCheck --check-prefix=TEST7 %s
+
+TEST7: ---
+TEST7-NEXT: mode: latency
+TEST7-NEXT: key:
+TEST7-NEXT: instructions:
+TEST7-NEXT: - 'LB X10 X10 i_0x0'
+
+# RUN: llvm-exegesis -mode=latency -mtriple=riscv64-unknown-linux --benchmark-phase=assemble-measured-code -opcode-name=LR_W_RL -mattr="+a" |& FileCheck --check-prefix=TEST8 %s
+
+TEST8: ---
+TEST8-NEXT: mode: latency
+TEST8-NEXT: key:
+TEST8-NEXT: instructions:
+TEST8-NEXT: - 'LR_W_RL X10 X10'
\ No newline at end of file
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s
new file mode 100644
index 00000000000000..b6ee3266cae6ca
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s
@@ -0,0 +1,11 @@
+# RUN: llvm-exegesis -mtriple=riscv64-unknown-linux -mode=latency --benchmark-phase=assemble-measured-code -mattr=+d -opcode-name=FADD_D |& FileCheck %s
+
+CHECK: ---
+CHECK-NEXT: mode: latency
+CHECK-NEXT: key:
+CHECK-NEXT: instructions:
+CHECK-NEXT: - 'FADD_D [[REG1:F[0-9]+_D]] [[REG2:F[0-9]+_D]] [[REG3:F[0-9]+_D]] i_0x7'
+CHECK-NEXT: config: ''
+CHECK-NEXT: register_initial_values:
+CHECK-DAG: - '[[REG1]]=0x0'
+CHECK-LAST: ...
diff --git a/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s b/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s
new file mode 100644
index 00000000000000..f0a114f648fa24
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/RISCV/latency-pre-assigned-register.s
@@ -0,0 +1,4 @@
+RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=LB -mtriple=riscv64-unknown-linux-gnu
+
+CHECK: Warning: Pre-assigned register prevented usage of self-aliasing strategy.
+
diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
index 92ab3a96d91e6b..2908ea80d0e471 100644
--- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp
+++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp
@@ -168,7 +168,15 @@ void BasicBlockFiller::addInstruction(const MCInst &Inst, const DebugLoc &DL) {
} else if (Op.isImm()) {
Builder.addImm(Op.getImm());
} else if (!Op.isValid()) {
- llvm_unreachable("Operand is not set");
+ std::string Message;
+ llvm::raw_string_ostream MessageOut(Message);
+ MessageOut << "Operand is not set: Instr: ";
+ Inst.dump_pretty(MessageOut, MCII->getName(Inst.getOpcode()));
+ MessageOut << "; OpIndex: " << OpIndex;
+ const MCOperandInfo &OperandInfo = MCID.operands()[OpIndex];
+ MessageOut << "; OpInfo.OperandType: "
+ << static_cast<uint32_t>(OperandInfo.OperandType);
+ report_fatal_error(Twine(Message));
} else {
llvm_unreachable("Not yet implemented");
}
diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
index 1db8472e99f7c9..4d5fc241fde0d9 100644
--- a/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
+++ b/llvm/tools/llvm-exegesis/lib/BenchmarkCode.h
@@ -17,6 +17,11 @@
namespace llvm {
namespace exegesis {
+struct ScratchMemoryStore {
+ unsigned Reg;
+ unsigned Offset;
+};
+
// A collection of instructions that are to be assembled, executed and measured.
struct BenchmarkCode {
BenchmarkKey Key;
diff --git a/llvm/tools/llvm-exegesis/lib/CMakeLists.txt b/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
index 414b49e5e021c2..bb201ed89e6c57 100644
--- a/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
+++ b/llvm/tools/llvm-exegesis/lib/CMakeLists.txt
@@ -12,6 +12,9 @@ endif()
if (LLVM_TARGETS_TO_BUILD MATCHES "Mips")
list(APPEND LLVM_EXEGESIS_TARGETS "Mips")
endif()
+if(LLVM_TARGETS_TO_BUILD MATCHES "RISCV" OR LLVM_EXPERIMENTAL_TARGETS_TO_BUILD MATCHES "RISCV")
+ list(APPEND LLVM_EXEGESIS_TARGETS "RISCV")
+endif()
set(LLVM_EXEGESIS_TARGETS ${LLVM_EXEGESIS_TARGETS} PARENT_SCOPE)
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
index fd156ee01e7ce5..9b5bfe3196dcda 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.cpp
@@ -57,6 +57,14 @@ const MCOperand &InstructionTemplate::getValueFor(const Operand &Op) const {
return getValueFor(Instr->Variables[Op.getVariableIndex()]);
}
+MCOperand &InstructionTemplate::getValueFor(unsigned OpIdx) {
+ return getValueFor(Instr->Variables[OpIdx]);
+}
+
+const MCOperand &InstructionTemplate::getValueFor(unsigned OpIdx) const {
+ return getValueFor(Instr->Variables[OpIdx]);
+}
+
bool InstructionTemplate::hasImmediateVariables() const {
return any_of(Instr->Variables, [this](const Variable &Var) {
return Instr->getPrimaryOperand(Var).isImmediate();
diff --git a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
index 7aca224302a1ff..85fcb4e908f017 100644
--- a/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
+++ b/llvm/tools/llvm-exegesis/lib/CodeTemplate.h
@@ -35,6 +35,8 @@ struct InstructionTemplate {
const MCOperand &getValueFor(const Variable &Var) const;
MCOperand &getValueFor(const Operand &Op);
const MCOperand &getValueFor(const Operand &Op) const;
+ MCOperand &getValueFor(unsigned OpIdx);
+ const MCOperand &getValueFor(unsigned OpIdx) const;
bool hasImmediateVariables() const;
const Instruction &getInstr() const { return *Instr; }
ArrayRef<MCOperand> getVariableValues() const { return VariableValues; }
@@ -133,6 +135,10 @@ struct CodeTemplate {
// the pointer to this memory is passed in to the function.
unsigned ScratchSpacePointerInReg = 0;
+ // Require to pre-store value of a given register (fisrt)
+ // to scratch memory with given offset (second)
+ SmallVector<std::pair<unsigned, unsigned>, 2> PreinitScratchMemory;
+
#if defined(__GNUC__) && (defined(__clang__) || LLVM_GNUC_PREREQ(8, 0, 0))
// FIXME: GCC7 bug workaround. Drop #if after GCC7 no longer supported.
private:
diff --git a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
index 17d09a1ec0cf34..d387251a687e6a 100644
--- a/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
+++ b/llvm/tools/llvm-exegesis/lib/LlvmState.cpp
@@ -45,6 +45,12 @@ Expected<LLVMState> LLVMState::Create(std::string TripleName,
if (CpuName == "native")
CpuName = std::string(sys::getHostCPUName());
+ if (CpuName.empty()) {
+ std::unique_ptr<MCSubtargetInfo> Empty_STI(
+ TheTarget->createMCSubtargetInfo(TripleName, "", ""));
+ CpuName = Empty_STI->getAllProcessorDescriptions().begin()->Key;
+ }
+
std::unique_ptr<MCSubtargetInfo> STI(
TheTarget->createMCSubtargetInfo(TripleName, CpuName, ""));
assert(STI && "Unable to create subtarget info!");
diff --git a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
index 9c926d1fc61124..7705d9af4057e8 100644
--- a/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+++ b/llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
@@ -89,17 +89,17 @@ const BitVector *BitVectorCache::getUnique(BitVector &&BV) const {
return Entry.get();
}
-Instruction::Instruction(const MCInstrDesc *Description, StringRef Name,
- SmallVector<Operand, 8> Operands,
- SmallVector<Variable, 4> Variables,
- const BitVector *ImplDefRegs,
- const BitVector *ImplUseRegs,
- const BitVector *AllDefRegs,
- const BitVector *AllUseRegs)
+Instruction::Instruction(
+ const MCInstrDesc *Description, StringRef Name,
+ SmallVector<Operand, 8> Operands, SmallVector<Variable, 4> Variables,
+ const BitVector *ImplDefRegs, const BitVector *ImplUseRegs,
+ const BitVector *AllDefRegs, const BitVector *AllUseRegs,
+ const BitVector *MemoryRegs, const BitVector *NotMemoryRegs)
: Description(*Description), Name(Name), Operands(std::move(Operands)),
Variables(std::move(Variables)), ImplDefRegs(*ImplDefRegs),
ImplUseRegs(*ImplUseRegs), AllDefRegs(*AllDefRegs),
- AllUseRegs(*AllUseRegs) {}
+ AllUseRegs(*AllUseRegs), MemoryRegs(*MemoryRegs),
+ NotMemoryRegs(*NotMemoryRegs) {}
std::unique_ptr<Instruction>
Instruction::create(const MCInstrInfo &InstrInfo,
@@ -166,6 +166,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
BitVector ImplUseRegs = RATC.emptyRegisters();
BitVector AllDefRegs = RATC.emptyRegisters();
BitVector AllUseRegs = RATC.emptyRegisters();
+ BitVector MemoryRegs = RATC.emptyRegisters();
+ BitVector NotMemoryRegs = RATC.emptyRegisters();
+
for (const auto &Op : Operands) {
if (Op.isReg()) {
const auto &AliasingBits = Op.getRegisterAliasing().aliasedBits();
@@ -177,6 +180,10 @@ Instruction::create(const MCInstrInfo &InstrInfo,
ImplDefRegs |= AliasingBits;
if (Op.isUse() && Op.isImplicit())
ImplUseRegs |= AliasingBits;
+ if (Op.isUse() && Op.isMemory())
+ MemoryRegs |= AliasingBits;
+ if (Op.isUse() && !Op.isMemory())
+ NotMemoryRegs |= AliasingBits;
}
}
// Can't use make_unique because constructor is private.
@@ -185,7 +192,9 @@ Instruction::create(const MCInstrInfo &InstrInfo,
std::move(Variables), BVC.getUnique(std::move(ImplDefRegs)),
BVC.getUnique(std::move(ImplUseRegs)),
BVC.getUnique(std::move(AllDefRegs)),
- BVC.getUnique(std::move(AllUseRegs))));
+ BVC.getUnique(std::move(AllUseRegs)),
+ BVC.getUnique(std::move(MemoryRegs)),
+ BVC.getUnique(std::move(NotMemoryRegs))));
}
const Operand &Instruction::getPrimaryOperand(const Variable &Var) const {
@@ -240,6 +249,12 @@ bool Instruction::hasAliasingRegisters(
...
[truncated]
|
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
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| namespace { | ||
|
|
||
| static cl::OptionCategory | ||
| RISCVBenchmarkOptions("llvm-exegesis benchmark RISCV options"); |
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Now it really isn't used. We made it with expansion in mind. Deleted in this commit
| else | ||
| continue; | ||
| } | ||
| // Not a known opcode name; should be an opcode name range. |
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Could we implement the parsing logics here as a custom command line parser for OpcodeName? https://llvm.org/docs/CommandLine.html#writing-a-custom-parser
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Addressed
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topperc
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| case RISCV::C_ADDI_NOP: | ||
| case RISCV::C_ADD_HINT: | ||
| case RISCV::C_SLLI_HINT: | ||
| AssignedValue = MCOperand::createReg(RISCV::X0); |
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Why does this need special cases when they already have a register class that says the register must be X0?
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In comment above the function described, that some function from RISC-V C extension require special registers, registers for such instructions described in register class, but X0 - reserved register (set in RISCVRegisterInfo.cpp), and here we need to set it explicitly.
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Can you use the register class information to detect that instead of hardcoding a list of instructions? Why are only some of the _HINT instructions here? Should C_LUI_HINT, C_LI_HINT, C_MV_HINT be listed here?
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The process of determining the operand for instructions generally occurs in the randomizeMCOperand function. This function receives ForbiddenRegs, common to all platform instructions. The list of allowed registers (AllowedRegs) excludes ForbiddenRegs. X0 belongs to ForbiddenRegs (since it is a special register), so it can never be used in generation. In the case of HINT instructions, we use non-standard operands that are generally prohibited. Therefore, it is necessary to set operands for these instructions in a special function.
Added processing of additional cases from llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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Is possible to ask MCInstrInfo for the MCInstrDesc for the opcode so you can get the declared register class for the instruction destination? Then use that to pick X2 or X0 instead of hardcoding a list of opcodes that needs to be maintained if a new instruction that writes X0/X2 is added.
| @@ -17,6 +17,11 @@ | |||
| namespace llvm { | |||
| namespace exegesis { | |||
|
|
|||
| struct ScratchMemoryStore { | |||
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Can you add docstring to this struct and its fields?
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Removed this structure, because it is not used
| @@ -166,6 +166,9 @@ Instruction::create(const MCInstrInfo &InstrInfo, | |||
| BitVector ImplUseRegs = RATC.emptyRegisters(); | |||
| BitVector AllDefRegs = RATC.emptyRegisters(); | |||
| BitVector AllUseRegs = RATC.emptyRegisters(); | |||
| BitVector MemoryRegs = RATC.emptyRegisters(); | |||
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It seems that MemoryRegs is not used. Do we need it?
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Not currently used, it was added in addition to NotMemoryRegs since they are all aliased registers together. Could be used in future
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I think we should remove it until it is used.
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Addressed
| CodeTemplates.push_back(std::move(CT)); | ||
| } | ||
|
|
||
| // TODO: implement more cases |
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What are the other cases besides !I.Description.mayLoad()? What was the reason we chose to implement only the I.Description.mayLoad() case for RISC-V support?
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Now case for I.Description.mayLoad() is enough to provide aliasing strategy for load operation in RISC-V. In future, maybe, we add some more cases for other strategies.
| @@ -55,6 +55,7 @@ class SnippetGenerator { | |||
| public: | |||
| struct Options { | |||
| unsigned MaxConfigsPerOpcode = 1; | |||
| std::optional<int64_t> InitImmValue; | |||
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Is this used anywhere?
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Now it really isn't used. We made it with expansion in mind. Deleted in this commit
|
|
||
| // Find register by name, 0 if not found. | ||
| virtual unsigned findRegisterByName(const StringRef RegName) const { | ||
| return 0; |
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Is it possible for a register to have the value 0? Why not RISCV::NoRegister for RISC-V? Thats what RISCVAsmParser::matchRegisterNameHelper returns when there is no match.
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| @@ -0,0 +1,3 @@ | |||
| RUN: llvm-exegesis -mode=latency --benchmark-phase=assemble-measured-code -opcode-name=LB -mtriple=riscv64-unknown-linux-gnu | |||
|
|
|||
| CHECK: Warning: Pre-assigned register prevented usage of self-aliasing strategy. | |||
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I am a bit confused by this test. What is the pre-assigned register that prevented usage of self-aliasing? I would expect a warning that no instructions were passed.
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This test was used previously, during implementing, now it is not used anymore, removed it, thanks for the catch.
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| @@ -160,12 +166,17 @@ struct Instruction { | |||
| const BitVector &ImplUseRegs; // The set of aliased implicit use registers. | |||
| const BitVector &AllDefRegs; // The set of all aliased def registers. | |||
| const BitVector &AllUseRegs; // The set of all aliased use registers. | |||
| const BitVector &MemoryRegs; // The set of all aliased memory use registers. | |||
| const BitVector | |||
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This formatting looks odd... maybe we could just put the comment above the line so that clang-format won't do anything funny?
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Addressed
|
Note: please don't forced push to update PR unless it's really necessary: https://llvm.org/docs/GitHub.html#updating-pull-requests |
| @@ -17,6 +17,11 @@ | |||
| namespace llvm { | |||
| namespace exegesis { | |||
|
|
|||
| struct ScratchMemoryStore { | |||
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This looks unused, did you mean to use it in PreinitScratchMemory ?
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It is really unused. Thanks for the catch!
| if (DefOpIt == I.Operands.end()) | ||
| return; | ||
|
|
||
| auto &DefOp = *DefOpIt; |
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avoid auto here for readability. getValueFor has a few overloads, it' not obvious which one is called.
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Addressed
| @@ -35,6 +35,8 @@ struct InstructionTemplate { | |||
| const MCOperand &getValueFor(const Variable &Var) const; | |||
| MCOperand &getValueFor(const Operand &Op); | |||
| const MCOperand &getValueFor(const Operand &Op) const; | |||
| MCOperand &getValueFor(unsigned OpIdx); | |||
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Having the same name for this overload is confusing: the two overloads for Variable and Operand are unambiguous thanks to the types, but this one is unclear as to whether we're talking about an operand or variable. getValueForOperandIdx ?
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Addressed
| } | ||
|
|
||
| // Find register by name, NoRegister if not found. | ||
| virtual unsigned findRegisterByName(const StringRef RegName) const = 0; |
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Why can't this be non-virtual and use RegNameToRegNoMapping ?
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Create default implementation for all platforms. Thank you!
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…pliant way Fixed some FileChecks in tests. Firstly found in PR89047 (llvm#89047 (comment))
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You need to add some REQUIRES to tests. @dybv-sc @AnastasiyaChernikova
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This reverts commit bc3eee1. These tests are failing because of no `REQUIRES`.
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Don't worry, I reverted this PR in bf62ea4. |
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@wangpc-pp, thanks! I've posted fix: #120419 |
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This patch also makes following amendments to core exegesis:
* Added distinction between regular registers aliasing check and
registers used as memory address in instruction.
* Added scratch memory space pointer register.
* General exegesis options were amended:
* mattr - new option to pass a list of enabled target features
Llvm-exegesis RISCV port is a result of team effort. Below everyone
involved listed.
Co-authored-by: Konstantin Vladimirov
<konstantin.vladimirov@syntacore.com>
Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Dmitry Bushev <dmitry.bushev@syntacore.com>
Co-authored-by: Mark Goncharov <mark.goncharov@syntacore.com>
Co-authored-by: Anastasiya Chernikova
<anastasiya.chernikova@syntacore.com>
Original pr: #89047
---------
Co-authored-by: Kazu Hirata <kazu@google.com>
This was referenced Jun 2, 2025
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This patch also makes following amendments to core exegesis:
Llvm-exegesis RISCV port is a result of team effort. Below everyone involved listed.
Co-authored-by: Konstantin Vladimirov konstantin.vladimirov@syntacore.com
Co-authored-by: Dmitrii Petrov dmitrii.petrov@syntacore.com
Co-authored-by: Dmitry Bushev dmitry.bushev@syntacore.com
Co-authored-by: Mark Goncharov mark.goncharov@syntacore.com
Co-authored-by: Anastasiya Chernikova anastasiya.chernikova@syntacore.com