[AMDGPU][MC] Enables sgpr or imm src1 for float VOP3 DPP, but excludi… #87382
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Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on GFX1150Plus The w32 and w64 _e64_dpp assembler only real instructions were unused, and erroneously constructed in a way that bugged parsing of the new instructions. They are removed. This patch is a follow up to PR llvm#87382
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…ng VOPC. Fixes support on GFX1150 and GFX12 where src1 of e64_dpp instructions should allow sgpr and imm operands. PR llvm#67461 added support for this with int operands, but it was missing a piece for float. Changing VOPC e64_dpp will be in a different patch because there is a bug preventing that change.
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Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on GFX1150Plus The w32 and w64 _e64_dpp assembler only real instructions were unused, and erroneously constructed in a way that bugged parsing of the new instructions. They are removed. This patch is a follow up to PR llvm#87382
Sisyph
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Allows src1 of VOP3 encoded VOPC to be an SGPR or inline immediate on GFX1150Plus The w32 and w64 _e64_dpp assembler only real instructions were unused, and erroneously constructed in a way that bugged parsing of the new instructions. They are removed. This patch is a follow up to PR #87382
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…ng VOPC.
Fixes support on GFX1150 and GFX12 where src1 of e64_dpp instructions should allow sgpr and imm operands.
PR #67461 added support for this with int operands, but it was missing a piece for float.
Changing VOPC e64_dpp will be in a different patch because there is a bug preventing that change.