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[PowerPC][AIX] Specify correct ABI alignment for double #144673

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4 changes: 2 additions & 2 deletions clang/lib/Basic/Targets/PPC.h
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Original file line number Diff line number Diff line change
Expand Up @@ -389,7 +389,7 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
: PPCTargetInfo(Triple, Opts) {
if (Triple.isOSAIX())
resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32-f64:32:64");
else if (Triple.getArch() == llvm::Triple::ppcle)
resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
else
Expand Down Expand Up @@ -448,7 +448,7 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {

if (Triple.isOSAIX()) {
// TODO: Set appropriate ABI for AIX platform.
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64";
DataLayout = "E-m:a-Fi64-i64:64-i128:128-n32:64-f64:32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
Expand Down
8 changes: 7 additions & 1 deletion llvm/lib/IR/AutoUpgrade.cpp
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Expand Up @@ -5926,7 +5926,13 @@ std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) {
if (Pos != size_t(-1))
Res.insert(Pos + I64.size(), I128);
}
return Res;
}

if (T.isPPC() && T.isOSAIX() && !DL.contains("f64:32:64") && !DL.empty()) {
size_t Pos = Res.find("-S128");
if (Pos == StringRef::npos)
Pos = Res.size();
Res.insert(Pos, "-f64:32:64");
}

if (!T.isX86())
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
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Expand Up @@ -192,6 +192,10 @@ static std::string getDataLayoutString(const Triple &T) {
else
Ret += "-n32";

// The ABI alignment for doubles on AIX is 4 bytes.
if (T.isOSAIX())
Ret += "-f64:32:64";

// Specify the vector alignment explicitly. For v256i1 and v512i1, the
// calculated alignment would be 256*alignment(i1) and 512*alignment(i1),
// which is 256 and 512 bytes - way over aligned.
Expand Down
152 changes: 70 additions & 82 deletions llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
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174 changes: 81 additions & 93 deletions llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
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Expand Up @@ -1012,22 +1012,18 @@ define void @call_test_stackarg_float() {
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfs 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
; ASM32PWR4-NEXT: li 10, 8
; ASM32PWR4-NEXT: lfd 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-NEXT: lwz 5, 76(1)
; ASM32PWR4-NEXT: lwz 11, 72(1)
; ASM32PWR4-NEXT: stw 5, 64(1)
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 10, 8
; ASM32PWR4-NEXT: stfd 2, 60(1)
; ASM32PWR4-NEXT: stfs 1, 56(1)
; ASM32PWR4-NEXT: stw 11, 60(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
Expand Down Expand Up @@ -1130,24 +1126,20 @@ define void @call_test_stackarg_float3() {
; ASM32PWR4-NEXT: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfd 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
; ASM32PWR4-NEXT: stfd 1, 72(1)
; ASM32PWR4-NEXT: lwz 10, 72(1)
; ASM32PWR4-NEXT: lfs 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lwz 4, 68(1)
; ASM32PWR4-NEXT: lwz 10, 72(1)
; ASM32PWR4-NEXT: lwz 11, 64(1)
; ASM32PWR4-NEXT: stw 4, 56(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: stfs 2, 60(1)
; ASM32PWR4-NEXT: stw 11, 52(1)
; ASM32PWR4-NEXT: stfd 1, 52(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
Expand Down Expand Up @@ -1570,99 +1562,95 @@ define void @caller_fpr_stack() {
; ASM32PWR4-LABEL: caller_fpr_stack:
; ASM32PWR4: # %bb.0: # %entry
; ASM32PWR4-NEXT: mflr 0
; ASM32PWR4-NEXT: stwu 1, -160(1)
; ASM32PWR4-NEXT: stwu 1, -144(1)
; ASM32PWR4-NEXT: lwz 3, L..C19(2) # @d15
; ASM32PWR4-NEXT: stw 0, 168(1)
; ASM32PWR4-NEXT: lwz 5, L..C20(2) # %const.1
; ASM32PWR4-NEXT: lwz 4, L..C21(2) # @f14
; ASM32PWR4-NEXT: lwz 4, L..C20(2) # @f14
; ASM32PWR4-NEXT: lwz 5, L..C21(2) # @f16
; ASM32PWR4-NEXT: stw 0, 152(1)
; ASM32PWR4-NEXT: lis 6, 16361
; ASM32PWR4-NEXT: ori 6, 6, 39321
; ASM32PWR4-NEXT: lfd 0, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C22(2) # @f16
; ASM32PWR4-NEXT: lwz 3, 0(3)
; ASM32PWR4-NEXT: stw 3, 140(1)
; ASM32PWR4-NEXT: li 3, 0
; ASM32PWR4-NEXT: stw 3, 60(1)
; ASM32PWR4-NEXT: lis 3, 16352
; ASM32PWR4-NEXT: stw 3, 56(1)
; ASM32PWR4-NEXT: lis 3, 13107
; ASM32PWR4-NEXT: ori 3, 3, 13107
; ASM32PWR4-NEXT: stw 3, 68(1)
; ASM32PWR4-NEXT: lis 3, 16355
; ASM32PWR4-NEXT: ori 3, 3, 13107
; ASM32PWR4-NEXT: stw 3, 64(1)
; ASM32PWR4-NEXT: lis 3, 26214
; ASM32PWR4-NEXT: ori 3, 3, 26214
; ASM32PWR4-NEXT: stw 3, 76(1)
; ASM32PWR4-NEXT: lis 3, 16358
; ASM32PWR4-NEXT: ori 3, 3, 26214
; ASM32PWR4-NEXT: stw 3, 72(1)
; ASM32PWR4-NEXT: lis 3, -26215
; ASM32PWR4-NEXT: ori 3, 3, 39322
; ASM32PWR4-NEXT: stw 3, 84(1)
; ASM32PWR4-NEXT: stw 3, 100(1)
; ASM32PWR4-NEXT: lis 3, 16313
; ASM32PWR4-NEXT: ori 3, 3, 39321
; ASM32PWR4-NEXT: stw 3, 96(1)
; ASM32PWR4-NEXT: lis 3, -15729
; ASM32PWR4-NEXT: ori 3, 3, 23593
; ASM32PWR4-NEXT: stw 3, 108(1)
; ASM32PWR4-NEXT: lis 3, 16316
; ASM32PWR4-NEXT: ori 3, 3, 10485
; ASM32PWR4-NEXT: stw 3, 104(1)
; ASM32PWR4-NEXT: lis 3, -5243
; ASM32PWR4-NEXT: ori 3, 3, 7864
; ASM32PWR4-NEXT: stw 3, 116(1)
; ASM32PWR4-NEXT: lis 3, 16318
; ASM32PWR4-NEXT: ori 3, 3, 47185
; ASM32PWR4-NEXT: stw 3, 112(1)
; ASM32PWR4-NEXT: lis 3, 2621
; ASM32PWR4-NEXT: ori 3, 3, 28836
; ASM32PWR4-NEXT: stw 3, 124(1)
; ASM32PWR4-NEXT: lis 3, 16320
; ASM32PWR4-NEXT: ori 3, 3, 41943
; ASM32PWR4-NEXT: stw 3, 120(1)
; ASM32PWR4-NEXT: lwz 3, L..C23(2) # %const.0
; ASM32PWR4-NEXT: lfd 2, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C24(2) # %const.2
; ASM32PWR4-NEXT: lwz 3, 0(4)
; ASM32PWR4-NEXT: lwz 4, 0(5)
; ASM32PWR4-NEXT: li 5, 0
; ASM32PWR4-NEXT: stw 5, 60(1)
; ASM32PWR4-NEXT: lis 5, 16352
; ASM32PWR4-NEXT: stw 5, 56(1)
; ASM32PWR4-NEXT: lis 5, 13107
; ASM32PWR4-NEXT: ori 5, 5, 13107
; ASM32PWR4-NEXT: stw 5, 68(1)
; ASM32PWR4-NEXT: lis 5, 16355
; ASM32PWR4-NEXT: ori 5, 5, 13107
; ASM32PWR4-NEXT: stw 5, 64(1)
; ASM32PWR4-NEXT: lis 5, 26214
; ASM32PWR4-NEXT: ori 5, 5, 26214
; ASM32PWR4-NEXT: stw 5, 76(1)
; ASM32PWR4-NEXT: lis 5, 16358
; ASM32PWR4-NEXT: ori 5, 5, 26214
; ASM32PWR4-NEXT: stw 5, 72(1)
; ASM32PWR4-NEXT: lis 5, -26215
; ASM32PWR4-NEXT: ori 5, 5, 39322
; ASM32PWR4-NEXT: stw 5, 84(1)
; ASM32PWR4-NEXT: stw 5, 100(1)
; ASM32PWR4-NEXT: lis 5, 16313
; ASM32PWR4-NEXT: ori 5, 5, 39321
; ASM32PWR4-NEXT: stw 5, 96(1)
; ASM32PWR4-NEXT: lis 5, -15729
; ASM32PWR4-NEXT: ori 5, 5, 23593
; ASM32PWR4-NEXT: stw 5, 108(1)
; ASM32PWR4-NEXT: lis 5, 16316
; ASM32PWR4-NEXT: ori 5, 5, 10485
; ASM32PWR4-NEXT: stw 5, 104(1)
; ASM32PWR4-NEXT: lis 5, -5243
; ASM32PWR4-NEXT: ori 5, 5, 7864
; ASM32PWR4-NEXT: stw 5, 116(1)
; ASM32PWR4-NEXT: lis 5, 16318
; ASM32PWR4-NEXT: ori 5, 5, 47185
; ASM32PWR4-NEXT: stw 6, 80(1)
; ASM32PWR4-NEXT: lis 6, -13108
; ASM32PWR4-NEXT: ori 6, 6, 52429
; ASM32PWR4-NEXT: stw 5, 112(1)
; ASM32PWR4-NEXT: lis 5, 2621
; ASM32PWR4-NEXT: ori 5, 5, 28836
; ASM32PWR4-NEXT: stw 6, 92(1)
; ASM32PWR4-NEXT: lis 6, 16364
; ASM32PWR4-NEXT: ori 6, 6, 52428
; ASM32PWR4-NEXT: stw 5, 124(1)
; ASM32PWR4-NEXT: lis 5, 16320
; ASM32PWR4-NEXT: ori 5, 5, 41943
; ASM32PWR4-NEXT: stw 6, 88(1)
; ASM32PWR4-NEXT: lwz 6, L..C22(2) # %const.0
; ASM32PWR4-NEXT: stw 5, 120(1)
; ASM32PWR4-NEXT: lwz 5, L..C23(2) # %const.1
; ASM32PWR4-NEXT: lfd 2, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C24(2) # %const.2
; ASM32PWR4-NEXT: lfd 3, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C25(2) # %const.3
; ASM32PWR4-NEXT: lfd 4, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C26(2) # %const.4
; ASM32PWR4-NEXT: lfd 4, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C26(2) # %const.4
; ASM32PWR4-NEXT: lfd 6, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C27(2) # %const.5
; ASM32PWR4-NEXT: lwz 4, 0(4)
; ASM32PWR4-NEXT: lfd 7, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C28(2) # %const.6
; ASM32PWR4-NEXT: lfd 7, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C28(2) # %const.6
; ASM32PWR4-NEXT: lfd 8, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C29(2) # %const.7
; ASM32PWR4-NEXT: stw 4, 128(1)
; ASM32PWR4-NEXT: lis 4, 16361
; ASM32PWR4-NEXT: ori 4, 4, 39321
; ASM32PWR4-NEXT: lfd 9, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C30(2) # %const.8
; ASM32PWR4-NEXT: lfd 9, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C30(2) # %const.8
; ASM32PWR4-NEXT: lfd 1, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C31(2) # %const.9
; ASM32PWR4-NEXT: stw 4, 80(1)
; ASM32PWR4-NEXT: lis 4, -13108
; ASM32PWR4-NEXT: lfd 11, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C32(2) # %const.10
; ASM32PWR4-NEXT: fmr 10, 1
; ASM32PWR4-NEXT: ori 4, 4, 52429
; ASM32PWR4-NEXT: lfd 11, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C32(2) # %const.10
; ASM32PWR4-NEXT: lfd 12, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C33(2) # %const.11
; ASM32PWR4-NEXT: stw 4, 92(1)
; ASM32PWR4-NEXT: lis 4, 16364
; ASM32PWR4-NEXT: ori 4, 4, 52428
; ASM32PWR4-NEXT: stfd 0, 152(1)
; ASM32PWR4-NEXT: stw 4, 88(1)
; ASM32PWR4-NEXT: lwz 4, 156(1)
; ASM32PWR4-NEXT: lfd 13, 0(3)
; ASM32PWR4-NEXT: lfd 13, 0(6)
; ASM32PWR4-NEXT: lfs 5, 0(5)
; ASM32PWR4-NEXT: lwz 3, 152(1)
; ASM32PWR4-NEXT: stw 4, 136(1)
; ASM32PWR4-NEXT: stw 3, 132(1)
; ASM32PWR4-NEXT: stfd 0, 132(1)
; ASM32PWR4-NEXT: stw 4, 140(1)
; ASM32PWR4-NEXT: stw 3, 128(1)
; ASM32PWR4-NEXT: bl .test_fpr_stack
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 160
; ASM32PWR4-NEXT: addi 1, 1, 144
; ASM32PWR4-NEXT: lwz 0, 8(1)
; ASM32PWR4-NEXT: mtlr 0
; ASM32PWR4-NEXT: blr
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/PowerPC/aix-emit-tracebacktable.ll
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Expand Up @@ -160,7 +160,7 @@ entry:
; CHECK-ASM-LABEL: .main:{{[[:space:]] *}}# %bb.0:
; CHECK-FUNC-LABEL: .csect .main[PR],5{{[[:space:]] *}}# %bb.0
; COMMON-NEXT: mflr 0
; COMMON: stw 0, 168(1)
; COMMON: stw 0, 152(1)
; COMMON: mtlr 0
; COMMON-NEXT: blr
; COMMON-NEXT: L..main0:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
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Expand Up @@ -29,8 +29,8 @@
%struct.anon = type <{ i32, double }>
@astruct = global [1 x %struct.anon] [%struct.anon <{ i32 1, double 7.000000e+00 }>], align 1

%struct.anon2 = type { double, i32 }
@bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1}], align 8
%struct.anon2 = type { double, i32, [4 x i8] }
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This is the LLVM IR clang would produce for struct { double x; int y; } after this change.

@bstruct = global [1 x %struct.anon2] [%struct.anon2 { double 7.000000e+00 , i32 1, [4 x i8] undef }], align 8

@a = common global i32 0, align 4
@b = common global i64 0, align 8
Expand Down
59 changes: 23 additions & 36 deletions llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg-mir.ll
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Expand Up @@ -115,23 +115,17 @@ define double @double_va_arg(double %a, ...) local_unnamed_addr {
; CHECK-NEXT: liveins: $f1, $r5, $r6, $r7, $r8, $r9, $r10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
; CHECK-NEXT: STW killed renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
; CHECK-NEXT: STW killed renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
; CHECK-NEXT: STW killed renamable $r7, 8, %fixed-stack.0 :: (store (s32), align 8)
; CHECK-NEXT: STW renamable $r5, 0, %fixed-stack.0 :: (store (s32) into %fixed-stack.0, align 16)
; CHECK-NEXT: STW renamable $r6, 4, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 4)
; CHECK-NEXT: STW killed renamable $r8, 12, %fixed-stack.0 :: (store (s32))
; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur2, align 16)
; CHECK-NEXT: STW killed renamable $r9, 16, %fixed-stack.0 :: (store (s32) into %fixed-stack.0 + 16, align 16)
; CHECK-NEXT: STW killed renamable $r10, 20, %fixed-stack.0 :: (store (s32))
; CHECK-NEXT: STW renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.1.arg2 :: (store (s32) into %ir.arg2)
; CHECK-NEXT: STW renamable $r5, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
; CHECK-NEXT: STW renamable $r6, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
; CHECK-NEXT: renamable $f0 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
; CHECK-NEXT: STW killed renamable $r5, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
; CHECK-NEXT: STW killed renamable $r6, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
entry:
%arg1 = alloca ptr, align 4
Expand Down Expand Up @@ -163,31 +157,24 @@ define double @double_stack_va_arg(double %one, double %two, double %three, doub
; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $f0 = LFD 0, %fixed-stack.0 :: (load (s64) from %ir.argp.cur142, align 16)
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f3, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f4, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f5, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f6, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f7, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f8, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f9, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f10, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f11, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f12, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f13, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, renamable $f0, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, renamable $f0, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f1, killed renamable $f0, implicit $rm
; CHECK-NEXT: renamable $r3 = ADDI %fixed-stack.0, 0
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.0.arg1 :: (store (s32) into %ir.arg1)
; CHECK-NEXT: renamable $r3 = LWZ 0, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142, align 16)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f1, killed renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f3, implicit $rm
; CHECK-NEXT: STW renamable $r3, 0, %stack.2 :: (store (s32) into %stack.2, align 8)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f4, implicit $rm
; CHECK-NEXT: renamable $r4 = LWZ 4, %fixed-stack.0 :: (load (s32) from %ir.argp.cur142 + 4)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f5, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f6, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f7, implicit $rm
; CHECK-NEXT: STW renamable $r4, 4, %stack.2 :: (store (s32) into %stack.2 + 4)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f8, implicit $rm
; CHECK-NEXT: renamable $f1 = LFD 0, %stack.2 :: (load (s64) from %stack.2)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f9, implicit $rm
; CHECK-NEXT: STW killed renamable $r3, 0, %stack.3 :: (store (s32) into %stack.3, align 8)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f10, implicit $rm
; CHECK-NEXT: STW killed renamable $r4, 4, %stack.3 :: (store (s32) into %stack.3 + 4)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f11, implicit $rm
; CHECK-NEXT: renamable $f2 = LFD 0, %stack.3 :: (load (s64) from %stack.3)
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f12, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f13, implicit $rm
; CHECK-NEXT: renamable $f0 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f2, renamable $f2, implicit $rm
; CHECK-NEXT: renamable $f1 = nofpexcept FADD killed renamable $f0, killed renamable $f1, implicit $rm
; CHECK-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
entry:
%arg1 = alloca ptr, align 4
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