[llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator"

[lakshayk-nv]

Implementing randomizeTargetMCOperand() for AArch64 that omitting OPERAND_UNKNOWN and OPERAND_PCREL to an immediate value based on opcode.

• Resolve illegal instructions error for MRS, MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF.
• Remove aarch64 guard in SnippetGenerator.cpp.

Please review: @sjoerdmeijer, @boomanaiden154, @davemgreen

[llvmbot]

@llvm/pr-subscribers-tools-llvm-exegesis

Author: Lakshay Kumar (lakshayk-nv)

Changes

Implementing randomizeTargetMCOperand() for AArch64 that omitting OPERAND_UNKNOWN and OPERAND_PCREL to an immediate value based on opcode.

---

Full diff: https://github.com/llvm/llvm-project/pull/142529.diff

2 Files Affected:

• (modified) llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp (+38)
• (modified) llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp (+8)

diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index a1eb5a46f21fc..285d888770a53 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -162,6 +162,10 @@ class ExegesisAArch64Target : public ExegesisTarget {
   ExegesisAArch64Target()
       : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
 
+  Error randomizeTargetMCOperand(
+      const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+      const BitVector &ForbiddenRegs) const override;
+
 private:
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
                                const APInt &Value) const override {
@@ -229,6 +233,40 @@ class ExegesisAArch64Target : public ExegesisTarget {
   }
 };
 
+Error ExegesisAArch64Target::randomizeTargetMCOperand(
+    const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+    const BitVector &ForbiddenRegs) const {
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  const auto OperandType = Op.getExplicitOperandInfo().OperandType;
+  // Introducing some illegal instructions for (15) a few opcodes
+  // TODO: Look into immediate values to be opcode specific
+  switch (OperandType) {
+    case MCOI::OperandType::OPERAND_UNKNOWN: {
+      unsigned Opcode = Instr.getOpcode();
+      switch (Opcode) {
+        case AArch64::MOVIv2s_msl:
+        case AArch64::MOVIv4s_msl:
+        case AArch64::MVNIv2s_msl:
+        case AArch64::MVNIv4s_msl:
+          AssignedValue = MCOperand::createImm(8); // or 16, as needed
+          return Error::success();
+        default:
+          AssignedValue = MCOperand::createImm(0);
+          return Error::success();
+      }
+    }
+    case MCOI::OperandType::OPERAND_PCREL:
+      AssignedValue = MCOperand::createImm(0);
+      return Error::success();
+    default:
+      break;
+  }
+
+  return make_error<Failure>(
+      Twine("Unimplemented operand type: MCOI::OperandType:")
+          .concat(Twine(static_cast<int>(OperandType))));
+}
+
 } // namespace
 
 static ExegesisTarget *getTheExegesisAArch64Target() {
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 04064ae1d8441..d4381c3b123f0 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -276,6 +276,14 @@ static Error randomizeMCOperand(const LLVMState &State,
     AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
     break;
   }
+  /// Omit unknown and pc-relative operands to imm value based on the instruction
+  // TODO: Neccesity of AArch64 guard ?
+#ifdef __aarch64__
+  case MCOI::OperandType::OPERAND_UNKNOWN:
+  case MCOI::OperandType::OPERAND_PCREL:
+    return State.getExegesisTarget().randomizeTargetMCOperand(
+        Instr, Var, AssignedValue, ForbiddenRegs);
+#endif
   default:
     break;
   }

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[boomanaiden154]

This also needs a test.

[boomanaiden154]

This sounds like a problem that should be fixed or at least better documented?

[lakshayk-nv]

Yes, We would like to support these instructions.
This patch in --mode=inverse_throughput for opcodes MRS, MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF exits with handled error of snippet crashed while running: Illegal instruction, they previously used to exits with error not all operands initialized by snippet generator`.

Working on correctly init operands for above mentioned opcodes, Will add commit in this PR for them.
Just wanted to state it explicitly, patch doesn't regress any working opcode.

[For completeness] Additionally, exegesis beforehand and with this patch too, throws illegal instruction in throughput mode, for these opcodes too (APAS, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, STGM, STZGM). Will look into them later.

[boomanaiden154]

What exactly does or 16 mean here?

[lakshayk-nv]

msl opcode asset for immediate values being 8 or 16. [Here](https://llvm.org/doxygen/AArch64MCCodeEmitter_8cpp_source.html#:~:text=assert((ShiftVal%20%3D%3D%208,705)

[davemgreen]

Ideally this would be marked as a OPERAND_IMMEDIATE with a range that tablegen understood, so that it could be used for validation of codegen and reused here.