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AMDGPU: Improve v8f16/v8bf16 copysign handling #142175

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merged 1 commit into from
May 31, 2025
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AMDGPU: Improve v8f16/v8bf16 copysign handling #142175

merged 1 commit into from
May 31, 2025

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@arsenm arsenm commented May 30, 2025

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arsenm commented May 30, 2025 •
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@arsenm arsenm marked this pull request as ready for review May 30, 2025 15:54
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llvmbot commented May 30, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Patch is 32.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/142175.diff

3 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+5-4)
  • (modified) llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll (+41-254)
  • (modified) llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll (+28-201)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 1c30d3f3bd883..ecfa6daf7803d 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -758,7 +758,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
 
     // Can do this in one BFI plus a constant materialize.
     setOperationAction(ISD::FCOPYSIGN,
-                       {MVT::v2f16, MVT::v2bf16, MVT::v4f16, MVT::v4bf16},
+                       {MVT::v2f16, MVT::v2bf16, MVT::v4f16, MVT::v4bf16,
+                        MVT::v8f16, MVT::v8bf16},
                        Custom);
 
     setOperationAction({ISD::FMAXNUM, ISD::FMINNUM}, MVT::f16, Custom);
@@ -5940,9 +5941,9 @@ SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
   EVT VT = Op.getValueType();
   assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16 ||
          VT == MVT::v4f32 || VT == MVT::v8i16 || VT == MVT::v8f16 ||
-         VT == MVT::v16i16 || VT == MVT::v16f16 || VT == MVT::v8f32 ||
-         VT == MVT::v16f32 || VT == MVT::v32f32 || VT == MVT::v32i16 ||
-         VT == MVT::v32f16);
+         VT == MVT::v8bf16 || VT == MVT::v16i16 || VT == MVT::v16f16 ||
+         VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32 ||
+         VT == MVT::v32i16 || VT == MVT::v32f16);
 
   auto [Lo0, Hi0] = DAG.SplitVectorOperand(Op.getNode(), 0);
   auto [Lo1, Hi1] = DAG.SplitVectorOperand(Op.getNode(), 1);
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 3bc1232ce3ed1..ab4cff2469467 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -1390,47 +1390,19 @@ define amdgpu_ps <4 x i32> @s_copysign_v8bf16(<8 x bfloat> inreg %arg_mag, <8 x
 ;
 ; GFX8-LABEL: s_copysign_v8bf16:
 ; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_movk_i32 s8, 0x7fff
+; GFX8-NEXT:    s_mov_b32 s8, 0x7fff7fff
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    s_lshr_b32 s7, s7, 16
-; GFX8-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX8-NEXT:    v_bfi_b32 v0, s8, v0, v1
-; GFX8-NEXT:    v_mov_b32_e32 v1, s3
-; GFX8-NEXT:    v_mov_b32_e32 v2, s7
-; GFX8-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s6
-; GFX8-NEXT:    s_lshr_b32 s3, s6, 16
-; GFX8-NEXT:    s_lshr_b32 s2, s2, 16
 ; GFX8-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; GFX8-NEXT:    v_mov_b32_e32 v2, s2
-; GFX8-NEXT:    v_mov_b32_e32 v3, s3
-; GFX8-NEXT:    v_bfi_b32 v2, s8, v2, v3
-; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-NEXT:    v_mov_b32_e32 v3, s5
-; GFX8-NEXT:    s_lshr_b32 s2, s5, 16
-; GFX8-NEXT:    s_lshr_b32 s1, s1, 16
 ; GFX8-NEXT:    v_bfi_b32 v2, s8, v2, v3
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
-; GFX8-NEXT:    v_mov_b32_e32 v4, s2
-; GFX8-NEXT:    v_bfi_b32 v3, s8, v3, v4
-; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v4, s4
-; GFX8-NEXT:    s_lshr_b32 s1, s4, 16
-; GFX8-NEXT:    s_lshr_b32 s0, s0, 16
 ; GFX8-NEXT:    v_bfi_b32 v3, s8, v3, v4
-; GFX8-NEXT:    v_mov_b32_e32 v4, s0
-; GFX8-NEXT:    v_mov_b32_e32 v5, s1
-; GFX8-NEXT:    v_bfi_b32 v4, s8, v4, v5
-; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_readfirstlane_b32 s0, v3
 ; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
@@ -1439,47 +1411,19 @@ define amdgpu_ps <4 x i32> @s_copysign_v8bf16(<8 x bfloat> inreg %arg_mag, <8 x
 ;
 ; GFX9-LABEL: s_copysign_v8bf16:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
+; GFX9-NEXT:    s_mov_b32 s8, 0x7fff7fff
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s3
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s7
-; GFX9-NEXT:    s_lshr_b32 s7, s7, 16
-; GFX9-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX9-NEXT:    v_bfi_b32 v0, s8, v0, v1
-; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_mov_b32_e32 v2, s7
-; GFX9-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s6
-; GFX9-NEXT:    s_lshr_b32 s3, s6, 16
-; GFX9-NEXT:    s_lshr_b32 s2, s2, 16
 ; GFX9-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; GFX9-NEXT:    v_mov_b32_e32 v2, s2
-; GFX9-NEXT:    v_mov_b32_e32 v3, s3
-; GFX9-NEXT:    v_bfi_b32 v2, s8, v2, v3
-; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s5
-; GFX9-NEXT:    s_lshr_b32 s2, s5, 16
-; GFX9-NEXT:    s_lshr_b32 s1, s1, 16
 ; GFX9-NEXT:    v_bfi_b32 v2, s8, v2, v3
-; GFX9-NEXT:    v_mov_b32_e32 v3, s1
-; GFX9-NEXT:    v_mov_b32_e32 v4, s2
-; GFX9-NEXT:    v_bfi_b32 v3, s8, v3, v4
-; GFX9-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX9-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s4
-; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
-; GFX9-NEXT:    s_lshr_b32 s0, s0, 16
 ; GFX9-NEXT:    v_bfi_b32 v3, s8, v3, v4
-; GFX9-NEXT:    v_mov_b32_e32 v4, s0
-; GFX9-NEXT:    v_mov_b32_e32 v5, s1
-; GFX9-NEXT:    v_bfi_b32 v4, s8, v4, v5
-; GFX9-NEXT:    v_and_b32_e32 v3, 0xffff, v3
-; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v3
 ; GFX9-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX9-NEXT:    v_readfirstlane_b32 s2, v1
@@ -1488,85 +1432,36 @@ define amdgpu_ps <4 x i32> @s_copysign_v8bf16(<8 x bfloat> inreg %arg_mag, <8 x
 ;
 ; GFX10-LABEL: s_copysign_v8bf16:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_mov_b32_e32 v0, s7
-; GFX10-NEXT:    s_lshr_b32 s7, s7, 16
+; GFX10-NEXT:    v_mov_b32_e32 v0, s4
+; GFX10-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX10-NEXT:    v_mov_b32_e32 v2, s6
-; GFX10-NEXT:    v_mov_b32_e32 v1, s7
-; GFX10-NEXT:    s_lshr_b32 s7, s6, 16
-; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, s3, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v3, s7
-; GFX10-NEXT:    s_lshr_b32 s3, s3, 16
-; GFX10-NEXT:    v_mov_b32_e32 v4, s5
-; GFX10-NEXT:    v_mov_b32_e32 v5, s4
-; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff, s3, v1
-; GFX10-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, s2, v2
-; GFX10-NEXT:    v_bfi_b32 v3, 0x7fff, s3, v3
-; GFX10-NEXT:    s_lshr_b32 s2, s5, 16
-; GFX10-NEXT:    s_lshr_b32 s3, s4, 16
-; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, s1, v4
-; GFX10-NEXT:    v_mov_b32_e32 v6, s2
-; GFX10-NEXT:    v_mov_b32_e32 v7, s3
-; GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, s0, v5
-; GFX10-NEXT:    s_lshr_b32 s1, s1, 16
-; GFX10-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX10-NEXT:    v_bfi_b32 v6, 0x7fff, s1, v6
-; GFX10-NEXT:    v_bfi_b32 v7, 0x7fff, s0, v7
-; GFX10-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_lshl_or_b32 v5, v7, 16, v5
-; GFX10-NEXT:    v_lshl_or_b32 v4, v6, 16, v4
-; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
-; GFX10-NEXT:    v_readfirstlane_b32 s0, v5
-; GFX10-NEXT:    v_readfirstlane_b32 s1, v4
+; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff7fff, s0, v0
+; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff7fff, s1, v1
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff7fff, s2, v2
+; GFX10-NEXT:    v_bfi_b32 v3, 0x7fff7fff, s3, v3
+; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX10-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX10-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX10-NEXT:    ; return to shader part epilog
 ;
 ; GFX11-LABEL: s_copysign_v8bf16:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    v_mov_b32_e32 v0, s7
-; GFX11-NEXT:    s_lshr_b32 s7, s7, 16
-; GFX11-NEXT:    v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s4
-; GFX11-NEXT:    v_mov_b32_e32 v1, s7
-; GFX11-NEXT:    s_lshr_b32 s7, s6, 16
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
 ; GFX11-NEXT:    v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX11-NEXT:    v_bfi_b32 v0, 0x7fff, s3, v0
-; GFX11-NEXT:    s_lshr_b32 s3, s3, 16
-; GFX11-NEXT:    v_bfi_b32 v4, 0x7fff, s1, v4
-; GFX11-NEXT:    v_bfi_b32 v1, 0x7fff, s3, v1
-; GFX11-NEXT:    s_lshr_b32 s3, s2, 16
-; GFX11-NEXT:    v_bfi_b32 v2, 0x7fff, s2, v2
-; GFX11-NEXT:    v_bfi_b32 v3, 0x7fff, s3, v3
-; GFX11-NEXT:    s_lshr_b32 s2, s5, 16
-; GFX11-NEXT:    s_lshr_b32 s3, s4, 16
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT:    v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s3
-; GFX11-NEXT:    v_bfi_b32 v5, 0x7fff, s0, v5
-; GFX11-NEXT:    s_lshr_b32 s1, s1, 16
-; GFX11-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX11-NEXT:    v_bfi_b32 v6, 0x7fff, s1, v6
-; GFX11-NEXT:    v_bfi_b32 v7, 0x7fff, s0, v7
-; GFX11-NEXT:    v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT:    v_and_b32_e32 v4, 0xffff, v4
-; GFX11-NEXT:    v_and_b32_e32 v2, 0xffff, v2
-; GFX11-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshl_or_b32 v5, v7, 16, v5
-; GFX11-NEXT:    v_lshl_or_b32 v4, v6, 16, v4
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_bfi_b32 v0, 0x7fff7fff, s0, v0
+; GFX11-NEXT:    v_bfi_b32 v1, 0x7fff7fff, s1, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_bfi_b32 v2, 0x7fff7fff, s2, v2
+; GFX11-NEXT:    v_bfi_b32 v3, 0x7fff7fff, s3, v3
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT:    v_readfirstlane_b32 s0, v5
-; GFX11-NEXT:    v_readfirstlane_b32 s1, v4
+; GFX11-NEXT:    v_readfirstlane_b32 s0, v0
+; GFX11-NEXT:    v_readfirstlane_b32 s1, v1
 ; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
 ; GFX11-NEXT:    v_readfirstlane_b32 s2, v2
-; GFX11-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX11-NEXT:    v_readfirstlane_b32 s3, v3
 ; GFX11-NEXT:    ; return to shader part epilog
   %out = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %arg_mag, <8 x bfloat> %arg_sign)
   %cast = bitcast <8 x bfloat> %out to <4 x i32>
@@ -2542,148 +2437,40 @@ define <8 x bfloat> @v_copysign_v8bf16(<8 x bfloat> %mag, <8 x bfloat> %sign) {
 ; GFX8-LABEL: v_copysign_v8bf16:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 16, v7
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v3
-; GFX8-NEXT:    s_movk_i32 s4, 0x7fff
-; GFX8-NEXT:    v_bfi_b32 v8, s4, v9, v8
-; GFX8-NEXT:    v_bfi_b32 v3, s4, v3, v7
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 16, v6
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
-; GFX8-NEXT:    v_bfi_b32 v7, s4, v9, v7
-; GFX8-NEXT:    v_bfi_b32 v2, s4, v2, v6
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v1
-; GFX8-NEXT:    v_bfi_b32 v6, s4, v9, v6
-; GFX8-NEXT:    v_bfi_b32 v1, s4, v1, v5
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 16, v0
-; GFX8-NEXT:    v_bfi_b32 v5, s4, v9, v5
+; GFX8-NEXT:    s_mov_b32 s4, 0x7fff7fff
 ; GFX8-NEXT:    v_bfi_b32 v0, s4, v0, v4
-; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v6
-; GFX8-NEXT:    v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v7
-; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_lshlrev_b32_e32 v4, 16, v8
-; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT:    v_bfi_b32 v1, s4, v1, v5
+; GFX8-NEXT:    v_bfi_b32 v2, s4, v2, v6
+; GFX8-NEXT:    v_bfi_b32 v3, s4, v3, v7
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_copysign_v8bf16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_movk_i32 s4, 0x7fff
-; GFX9-NEXT:    v_bfi_b32 v8, s4, v3, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT:    v_bfi_b32 v3, s4, v3, v7
-; GFX9-NEXT:    v_bfi_b32 v7, s4, v2, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT:    v_bfi_b32 v2, s4, v2, v6
-; GFX9-NEXT:    v_bfi_b32 v6, s4, v1, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v5
-; GFX9-NEXT:    v_bfi_b32 v5, s4, v0, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT:    s_mov_b32 s4, 0x7fff7fff
 ; GFX9-NEXT:    v_bfi_b32 v0, s4, v0, v4
-; GFX9-NEXT:    s_mov_b32 s4, 0x5040100
-; GFX9-NEXT:    v_perm_b32 v0, v0, v5, s4
-; GFX9-NEXT:    v_perm_b32 v1, v1, v6, s4
-; GFX9-NEXT:    v_perm_b32 v2, v2, v7, s4
-; GFX9-NEXT:    v_perm_b32 v3, v3, v8, s4
+; GFX9-NEXT:    v_bfi_b32 v1, s4, v1, v5
+; GFX9-NEXT:    v_bfi_b32 v2, s4, v2, v6
+; GFX9-NEXT:    v_bfi_b32 v3, s4, v3, v7
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_copysign_v8bf16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_bfi_b32 v8, 0x7fff, v3, v7
-; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT:    v_bfi_b32 v9, 0x7fff, v2, v6
-; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v5
-; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v4
-; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 16, v0
-; GFX10-NEXT:    v_lshrrev_b32_e32 v13, 16, v1
-; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v5
-; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v4
-; GFX10-NEXT:    v_bfi_b32 v4, 0x7fff, v12, v11
-; GFX10-NEXT:    v_bfi_b32 v5, 0x7fff, v13, v10
-; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v6
-; GFX10-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v7
-; GFX10-NEXT:    v_perm_b32 v0, v4, v0, 0x5040100
-; GFX10-NEXT:    v_perm_b32 v1, v5, v1, 0x5040100
-; GFX10-NEXT:    v_perm_b32 v2, v2, v9, 0x5040100
-; GFX10-NEXT:    v_perm_b32 v3, v3, v8, 0x5040100
+; GFX10-NEXT:    v_bfi_b32 v0, 0x7fff7fff, v0, v4
+; GFX10-NEXT:    v_bfi_b32 v1, 0x7fff7fff, v1, v5
+; GFX10-NEXT:    v_bfi_b32 v2, 0x7fff7fff, v2, v6
+; GFX10-NEXT:    v_bfi_b32 v3, 0x7fff7fff, v3, v7
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 ;
-; GFX11TRUE16-LABEL: v_copysign_v8bf16:
-; GFX11TRUE16:       ; %bb.0:
-; GFX11TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v8.l, v3.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v9.l, v7.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v3.l, v3.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v7.l, v7.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v10.l, v2.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v11.l, v6.l
-; GFX11TRUE16-NEXT:    v_bfi_b32 v8, 0x7fff, v8, v9
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h
-; GFX11TRUE16-NEXT:    v_bfi_b32 v7, 0x7fff, v3, v7
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v9.l, v1.l
-; GFX11TRUE16-NEXT:    v_bfi_b32 v3, 0x7fff, v10, v11
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v10.l, v5.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v11.l, v0.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v12.l, v4.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v4.l, v4.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v1.l, v1.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v5.l, v5.h
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v6.l, v6.h
-; GFX11TRUE16-NEXT:    v_bfi_b32 v11, 0x7fff, v11, v12
-; GFX11TRUE16-NEXT:    v_bfi_b32 v4, 0x7fff, v0, v4
-; GFX11TRUE16-NEXT:    v_bfi_b32 v9, 0x7fff, v9, v10
-; GFX11TRUE16-NEXT:    v_bfi_b32 v5, 0x7fff, v1, v5
-; GFX11TRUE16-NEXT:    v_bfi_b32 v6, 0x7fff, v2, v6
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v0.l, v11.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v0.h, v4.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v1.l, v9.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v1.h, v5.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v2.l, v3.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v2.h, v6.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v3.l, v8.l
-; GFX11TRUE16-NEXT:    v_mov_b16_e32 v3.h, v7.l
-; GFX11TRUE16-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: v_copysign_v8bf16:
-; GFX11FAKE16:       ; %bb.0:
-; GFX11FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT:    v_bfi_b32 v8, 0x7fff, v3, v7
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 16, v7
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
-; GFX11FAKE16-NEXT:    v_bfi_b32 v9, 0x7fff, v2, v6
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v6
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v10, 16, v5
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v11, 16, v4
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v12, 16, v0
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v13, 16, v1
-; GFX11FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
-; GFX11FAKE16-NEXT:    v_bfi_b32 v1, 0x7fff, v1, v5
-; GFX11FAKE16-NEXT:    v_bfi_b32 v0, 0x7fff, v0, v4
-; GFX11FAKE16-NEXT:    v_bfi_b32 v4, 0x7fff, v12, v11
-; GFX11FAKE16-NEXT:    v_bfi_b32 v5, 0x7fff, v13, v10
-; GFX11FAKE16-NEXT:    v_bfi_b32 v2, 0x7fff, v2, v6
-; GFX11FAKE16-NEXT:    v_bfi_b32 v3, 0x7fff, v3, v7
-; GFX11FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT:    v_perm_b32 v0, v4, v0, 0x5040100
-; GFX11FAKE16-NEXT:    v_perm_b32 v1, v5, v1, 0x5040100
-; GFX11FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11FAKE16-NEXT:    v_perm_b32 v2, v2, v9, 0x5040100
-; GFX11FAKE16-NEXT:    v_perm_b32 v3, v3, v8, 0x5040100
-; GFX11FAKE16-NEXT:    s_setpc_b64 s[30:31]
+; GFX11-LABEL: v_copysign_v8bf16:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT:    v_bfi_b32 v0, 0x7fff7fff, v0, v4
+; GFX11-NEXT:    v_bfi_b32 v1, 0x7fff7fff, v1, v5
+; GFX11-NEXT:    v_bfi_b32 v2, 0x7fff7fff, v2, v6
+; GFX11-NEXT:    v_bfi_b32 v3, 0x7fff7fff, v3, v7
+; GFX11-NEXT:    s_setpc_b64 s[30:31]
   %result = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %mag, <8 x bfloat> %sign)
   ret <8 x bfloat> %result
 }
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index ee706df4c01d7..546dc3de20e41 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -1578,47 +1578,19 @@ define amdgpu_ps <4 x i32> @s_copysign_v8f16(<8 x half> inreg %arg_mag, <8 x hal
 ;
 ; VI-LABEL: s_copysign_v8f16:
 ; VI:       ; %bb.0:
-; VI-NEXT:    s_movk_i32 s8, 0x7fff
+; VI-NEXT:    s_mov_b32 s8, 0x7fff7fff
 ; VI-NEXT:    v_mov_b32_e32 v0, s3
 ; VI-NEXT:    v_mov_b32_e32 v1, s7
-; VI-NEXT:    s_lshr_b32 s7, s7, 16
-; VI-NEXT:    s_lshr_b32 s3, s3, 16
 ; VI-NEXT:    v_bfi_b32 v0, s8, v0, v1
-; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_mov_b32_e32 v2, s7
-; VI-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; VI-NEXT:    v_mov_b32_e32 v1, s2
 ; VI-NEXT:    v_mov_b32_e32 v2, s6
-; VI-NEXT:    s_lshr_b32 s3, s6, 16
-; VI-NEXT:    s_lshr_b32 s2, s2, 16
 ; VI-NEXT:    v_bfi_b32 v1, s8, v1, v2
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    v_bfi_b32 v2, s8, v2, v3
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 ...
[truncated]

@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v8f16-v8bf16-copysign-lowering branch from 196b010 to 883a508 Compare May 30, 2025 15:58
@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v4f16-v4bf16-copysign-lowering branch from f46d45d to acbd632 Compare May 30, 2025 15:58
@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v4f16-v4bf16-copysign-lowering branch from acbd632 to 7fc1968 Compare May 30, 2025 18:04
@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v8f16-v8bf16-copysign-lowering branch from 883a508 to d94e349 Compare May 30, 2025 18:05
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arsenm commented May 31, 2025 •
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  • May 31, 5:58 AM UTC: A user started a stack merge that includes this pull request via Graphite.
  • May 31, 6:10 AM UTC: Graphite rebased this pull request as part of a merge.
  • May 31, 6:13 AM UTC: Graphite rebased this pull request as part of a merge.
  • May 31, 6:15 AM UTC: @arsenm merged this pull request with Graphite.

@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v4f16-v4bf16-copysign-lowering branch from 7fc1968 to cf9576c Compare May 31, 2025 06:07
Base automatically changed from users/arsenm/amdgpu/improve-v4f16-v4bf16-copysign-lowering to main May 31, 2025 06:09
@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v8f16-v8bf16-copysign-lowering branch from d94e349 to 42f5f13 Compare May 31, 2025 06:10
@arsenm arsenm force-pushed the users/arsenm/amdgpu/improve-v8f16-v8bf16-copysign-lowering branch from 42f5f13 to aa7ccbf Compare May 31, 2025 06:12
@arsenm arsenm merged commit ffee01e into main May 31, 2025
6 of 11 checks passed
@arsenm arsenm deleted the users/arsenm/amdgpu/improve-v8f16-v8bf16-copysign-lowering branch May 31, 2025 06:15
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