Skip to content

[RISCV] add Double Trap extensions requires Zicsr #141016

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
May 22, 2025
Merged

[RISCV] add Double Trap extensions requires Zicsr #141016

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -922,9 +922,9 @@ def FeatureStdExtSscsrind
: RISCVExtension<1, 0, "Indirect CSR Access Supervisor Level">;

def FeatureStdExtSmdbltrp
: RISCVExtension<1, 0, "Double Trap Machine Level">;
: RISCVExtension<1, 0, "Double Trap Machine Level", [FeatureStdExtZicsr]>;
def FeatureStdExtSsdbltrp
: RISCVExtension<1, 0, "Double Trap Supervisor Level">;
: RISCVExtension<1, 0, "Double Trap Supervisor Level", [FeatureStdExtZicsr]>;

def FeatureStdExtSmepmp
: RISCVExtension<1, 0, "Enhanced Physical Memory Protection">;
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -496,8 +496,8 @@
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
; RV32SMDBLTRP: .attribute 5, "rv32i2p1_smdbltrp1p0"
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_ssdbltrp1p0"
; RV32SMDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_smdbltrp1p0"
; RV32SSDBLTRP: .attribute 5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
; RV32SMCNTRPMF: .attribute 5, "rv32i2p1_smcntrpmf1p0"
Expand Down Expand Up @@ -653,8 +653,8 @@
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
; RV64SMDBLTRP: .attribute 5, "rv64i2p1_smdbltrp1p0"
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_ssdbltrp1p0"
; RV64SMDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_smdbltrp1p0"
; RV64SSDBLTRP: .attribute 5, "rv64i2p1_zicsr2p0_ssdbltrp1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
; RV64SMCNTRPMF: .attribute 5, "rv64i2p1_smcntrpmf1p0"
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/attribute-arch.s
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -331,10 +331,10 @@
# CHECK: attribute 5, "rv32i2p1_sscsrind1p0"

.attribute arch, "rv32i_smdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_smdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_smdbltrp1p0"

.attribute arch, "rv32i_ssdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_ssdbltrp1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_ssdbltrp1p0"

.attribute arch, "rv32i_smcdeleg1p0"
# CHECK: attribute 5, "rv32i2p1_smcdeleg1p0"
Expand Down
Loading