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[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation #139993

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[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation #139993

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[RISCV] Move RISCVIndirectBranchTracking before Branch Relaxation
jaidTw May 5, 2025
be3cebd
fixup! Add comment
jaidTw May 15, 2025
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5 changes: 4 additions & 1 deletion llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -570,6 +570,10 @@ void RISCVPassConfig::addPreEmitPass() {
addPass(createMachineCopyPropagationPass(true));
if (TM->getOptLevel() >= CodeGenOptLevel::Default)
addPass(createRISCVLateBranchOptPass());
// The IndirectBranchTrackingPass inserts lpad and could have changed the
// basic block alignment. It must be done before Branch Relaxation to
// prevent the adjusted offset exceeding the branch range.
addPass(createRISCVIndirectBranchTrackingPass());
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Please can you add your message as a comment before this line? Correctly handling late passes with these kinds of target-specific dependencies is difficult, documenting the relative ordering constraints will help with future maintenance.

I don't expect a comment for every pass added, but given you know the reasoning for this ordering, we can write it down.

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Added

addPass(&BranchRelaxationPassID);
addPass(createRISCVMakeCompressibleOptPass());
}
Expand All @@ -581,7 +585,6 @@ void RISCVPassConfig::addPreEmitPass2() {
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
}
addPass(createRISCVIndirectBranchTrackingPass());
addPass(createRISCVExpandPseudoPass());

// Schedule the expansion of AMOs at the last possible moment, avoiding the
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/O0-pipeline.ll
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Expand Up @@ -62,6 +62,7 @@
; CHECK-NEXT: Insert fentry calls
; CHECK-NEXT: Insert XRay ops
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
Expand All @@ -73,7 +74,6 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/O3-pipeline.ll
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Expand Up @@ -195,6 +195,7 @@
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: RISC-V Late Branch Optimisation Pass
; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: RISC-V Make Compressible
; CHECK-NEXT: Contiguously Lay Out Funclets
Expand All @@ -210,7 +211,6 @@
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISC-V Zcmp move merging pass
; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
; CHECK-NEXT: RISC-V Indirect Branch Tracking
; CHECK-NEXT: RISC-V pseudo instruction expansion pass
; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
; CHECK-NEXT: Unpack machine instruction bundles
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