[Hexagon] shouldForceRelocation: check MCValue::Specifier

[quic-areg]

Hexagon follow-up to 38c3ad3.

[llvmbot]

@llvm/pr-subscribers-backend-hexagon

@llvm/pr-subscribers-mc

Author: None (quic-areg)

Changes

Hexagon follow-up to 38c3ad3.

---

Full diff: https://github.com/llvm/llvm-project/pull/139948.diff

2 Files Affected:

• (modified) llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp (+2-1)
• (added) llvm/test/MC/Hexagon/reloc-addends.s (+56)

diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 9f4a2fd539fa9..99ef12a2dd5b9 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -21,6 +21,7 @@
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCObjectWriter.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/EndianStream.h"
@@ -322,7 +323,7 @@ class HexagonAsmBackend : public MCAsmBackend {
         // Leave these relocations alone as they are used for EH.
         return false;
     }
-    return false;
+    return Target.getSpecifier();
   }
 
   /// getFixupKindNumBytes - The number of bytes the fixup may change.
diff --git a/llvm/test/MC/Hexagon/reloc-addends.s b/llvm/test/MC/Hexagon/reloc-addends.s
new file mode 100644
index 0000000000000..b7168cb522e28
--- /dev/null
+++ b/llvm/test/MC/Hexagon/reloc-addends.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc -triple=hexagon -mv73 -filetype=obj %s | llvm-readobj -r - | FileCheck %s
+
+# This checks various combinations of relocation addends.  Several cases below
+# had been incorrect.
+
+{
+  call a
+}
+#CHECK: R_HEX_B22_PCREL a 0x0
+
+## Expect .Lb+4
+{
+  if (p0) jump ##.Lb
+}
+{
+  p0 = !cmp.gt(r2, #-1)
+  p0 = sfclass(r2, #0xe)
+  if (!p0.new) jump:t c
+}
+#CHECK: R_HEX_B32_PCREL_X c 0x8
+#CHECK: R_HEX_B15_PCREL_X c 0xC
+
+{
+  if (!p0) jump d
+  if (p0) jump d
+}
+#CHECK: R_HEX_B32_PCREL_X d 0x0
+#CHECK: R_HEX_B15_PCREL_X d 0x4
+#CHECK: R_HEX_B32_PCREL_X d 0x8
+#CHECK: R_HEX_B15_PCREL_X d 0xC
+{
+  if (!p0) jump e
+  jump .Lb
+}
+#CHECK: R_HEX_B32_PCREL_X e 0x0
+#CHECK: R_HEX_B15_PCREL_X e 0x4
+.Lb:
+
+{
+r0 = add(pc, ##foo@PCREL)
+if (!p0) jump f
+}
+#CHECK: R_HEX_B32_PCREL_X foo 0x0
+#CHECK: R_HEX_6_PCREL_X foo 0x4
+#CHECK: R_HEX_B32_PCREL_X f 0x8
+#CHECK: R_HEX_B15_PCREL_X f 0xC
+
+{
+r0 = add(pc, ##.Lx@PCREL)
+if (!p0) jump __hexagon_sqrtf
+}
+.Lx:
+#CHECK: R_HEX_B32_PCREL_X .text
+#CHECK: R_HEX_6_PCREL_X .text
+#CHECK: R_HEX_B32_PCREL_X __hexagon_sqrtf 0x8
+#CHECK: R_HEX_B15_PCREL_X __hexagon_sqrtf 0xC