[MIPS] Add FeatureMSA to i6400 and i6500 cores #134985
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i6400 and i6500 cores support MIPS SIMD Architecture (MSA) instructions
mgoudar
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mshockwave
reviewed
Apr 9, 2025
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CI has reported an error:
Exit Code: 2
Command Output (stderr):
--
/var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/llc -mtriple=mips-elf -mcpu=i6500 < /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/test/CodeGen/Mips/msa/i6500.ll | /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/FileCheck /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/test/CodeGen/Mips/msa/i6500.ll --check-prefix=MIPS32 # RUN: at line 3
+ /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/llc -mtriple=mips-elf -mcpu=i6500
+ /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/FileCheck /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/test/CodeGen/Mips/msa/i6500.ll --check-prefix=MIPS32
Cannot handle this ValVT.
UNREACHABLE executed at /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Target/Mips/MipsISelLowering.cpp:3119!
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0. Program arguments: /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/llc -mtriple=mips-elf -mcpu=i6500
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'MIPS DAG->DAG Pattern Instruction Selection' on function '@llvm_mips_dlsa_test'
#0 0x00005d08c95dee68 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Support/Unix/Signals.inc:804:13
#1 0x00005d08c95dc99e llvm::sys::RunSignalHandlers() /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Support/Signals.cpp:106:18
#2 0x00005d08c95df4f1 SignalHandler(int, siginfo_t*, void*) (/var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/bin/llc+0x74b54f1)
#3 0x00007e830e867520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
#4 0x00007e830e8bb9fc pthread_kill (/lib/x86_64-linux-gnu/libc.so.6+0x969fc)
#5 0x00007e830e867476 gsignal (/lib/x86_64-linux-gnu/libc.so.6+0x42476)
#6 0x00007e830e84d7f3 abort (/lib/x86_64-linux-gnu/libc.so.6+0x287f3)
#7 0x00005d08c9549910 llvm::install_out_of_memory_new_handler() /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Support/ErrorHandling.cpp:195:0
#8 0x00005d08c74ef031 CC_MipsO32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&, llvm::ArrayRef<unsigned short>) /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Target/Mips/MipsISelLowering.cpp:3099:7
#9 0x00005d08c74e3284 CC_MipsO32_FP /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/lib/Target/Mips/MipsGenCallingConv.inc:381:9
#10 0x00005d08c74e3284 CC_Mips_FixedArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/build/lib/Target/Mips/MipsGenCallingConv.inc:581:10
#11 0x00005d08c8496026 llvm::CCState::AnalyzeFormalArguments(llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, bool (*)(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&)) /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/CodeGen/CallingConvLower.cpp:92:9
#12 0x00005d08c74e9d80 getStackSize /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/include/llvm/CodeGen/CallingConvLower.h:245:42
#13 0x00005d08c74e9d80 llvm::MipsTargetLowering::LowerFormalArguments(llvm::SDValue, unsigned int, bool, llvm::SmallVectorImpl<llvm::ISD::InputArg> const&, llvm::SDLoc const&, llvm::SelectionDAG&, llvm::SmallVectorImpl<llvm::SDValue>&) const /var/lib/buildkite-agent/builds/linux-56-59b8f5d88-h94vh-1/llvm-project/github-pull-requests/llvm/lib/Target/Mips/MipsISelLowering.cpp:3798:35
mshockwave
reviewed
Apr 9, 2025
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just a non-blocking suggestion: it'll be nice if you test individual CPU's features like https://github.com/llvm/llvm-project/blob/main/clang/test/Driver/riscv-cpus.c
llvm/test/CodeGen/Mips/msa/i6500.ll
Outdated
| @@ -0,0 +1,69 @@ | |||
| ; Test the MSA intrinsics that are encoded with the SPECIAL instruction format. | |||
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Could we use update_llc_test_checks.py to maintain this test?
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I have written driver test mips-cpus.c instead of codegen as you suggested.
as mips-cpus.c test, we need to enable MSA feature via -mmsa flag. I think we need to enable this as part of i6500 cpu flag by default via driver. please suggest.
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I have enabled MSA feature from driver also when -mcpu i6500/i6400 is specified. Also I have added codegen test to verify MSA instructions when i650/i6400 cpu is specified. please review
yes. let me check it |
Also remove codegen test i6500.ll
llvmbot
added
clang
|
@llvm/pr-subscribers-clang Author: Mallikarjuna Gouda (mgoudar) ChangesEnable 'FeatureMSA' for MIPS i6400 and i6500 cpu. MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default. Full diff: https://github.com/llvm/llvm-project/pull/134985.diff 2 Files Affected:
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
new file mode 100644
index 0000000000000..effb5ef60166a
--- /dev/null
+++ b/clang/test/Driver/mips-cpus.c
@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck -check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
+// MCPU-I6400-SAME: "-target-feature" "+msa"
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck -check-prefix=MCPU-I6500 %s
+// MCPU-I6500: "-target-cpu" "i6500"
+// MCPU-I6500-SAME: "-target-feature" "+msa"
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
- "MIPS I6400 Processor", [FeatureMips64r6]>;
+ "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
- "MIPS I6500 Processor", [FeatureMips64r6]>;
+ "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
|
|
@llvm/pr-subscribers-clang-driver Author: Mallikarjuna Gouda (mgoudar) ChangesEnable 'FeatureMSA' for MIPS i6400 and i6500 cpu. MIPS i6400 and i6500 cores implements MSA (MIPS SIMD ARCHITECTURE) by default. Full diff: https://github.com/llvm/llvm-project/pull/134985.diff 2 Files Affected:
diff --git a/clang/test/Driver/mips-cpus.c b/clang/test/Driver/mips-cpus.c
new file mode 100644
index 0000000000000..effb5ef60166a
--- /dev/null
+++ b/clang/test/Driver/mips-cpus.c
@@ -0,0 +1,9 @@
+// Check target CPUs are correctly passed.
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck -check-prefix=MCPU-I6400 %s
+// MCPU-I6400: "-target-cpu" "i6400"
+// MCPU-I6400-SAME: "-target-feature" "+msa"
+
+// RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6500 -mmsa | FileCheck -check-prefix=MCPU-I6500 %s
+// MCPU-I6500: "-target-cpu" "i6500"
+// MCPU-I6500-SAME: "-target-feature" "+msa"
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 43a5ae8133d83..ca3df1fd94144 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
- "MIPS I6400 Processor", [FeatureMips64r6]>;
+ "MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;
def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
- "MIPS I6500 Processor", [FeatureMips64r6]>;
+ "MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;
class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
|
mshockwave
reviewed
Apr 18, 2025
| // Check target CPUs are correctly passed. | ||
|
|
||
| // RUN: %clang --target=mips64 -### -c %s 2>&1 -mcpu=i6400 -mmsa | FileCheck -check-prefix=MCPU-I6400 %s | ||
| // MCPU-I6400: "-target-cpu" "i6400" |
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usually we will check all the features implied by this CPU. Not sure if this is practical in your case though.
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I modified test to verify abicalls feature as well. I see that mips-features.c test available to verify other features based on the options
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MIPS i6400 and i6500 cores implements and enables MSA (MIPS SIMD ARCHITECTURE) by default.