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[AArch64] Use ArrayRef::slice (NFC) #133862

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merged 1 commit into from
Apr 1, 2025
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[AArch64] Use ArrayRef::slice (NFC) #133862

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17 changes: 8 additions & 9 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1476,8 +1476,7 @@ void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,

// Form a REG_SEQUENCE to force register allocation.
unsigned Vec0Off = ExtOff + 1;
SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
N->op_begin() + Vec0Off + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(Vec0Off, NumVecs));
SDValue RegSeq = createQTuple(Regs);

SmallVector<SDValue, 6> Ops;
Expand Down Expand Up @@ -1863,7 +1862,7 @@ void AArch64DAGToDAGISel::SelectWhilePair(SDNode *N, unsigned Opc) {
void AArch64DAGToDAGISel::SelectCVTIntrinsic(SDNode *N, unsigned NumVecs,
unsigned Opcode) {
EVT VT = N->getValueType(0);
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(1, NumVecs));
SDValue Ops = createZTuple(Regs);
SDLoc DL(N);
SDNode *Intrinsic = CurDAG->getMachineNode(Opcode, DL, MVT::Untyped, Ops);
Expand Down Expand Up @@ -2072,7 +2071,7 @@ void AArch64DAGToDAGISel::SelectClamp(SDNode *N, unsigned NumVecs,
SDLoc DL(N);
EVT VT = N->getValueType(0);

SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(1, NumVecs));
SDValue Zd = createZMulTuple(Regs);
SDValue Zn = N->getOperand(1 + NumVecs);
SDValue Zm = N->getOperand(2 + NumVecs);
Expand Down Expand Up @@ -2242,7 +2241,7 @@ void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs,
SDLoc dl(N);

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(2, NumVecs));
SDValue RegSeq = createZTuple(Regs);

// Optimize addressing mode.
Expand Down Expand Up @@ -2287,7 +2286,7 @@ void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,

// Form a REG_SEQUENCE to force register allocation.
bool Is128Bit = VT.getSizeInBits() == 128;
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(1, NumVecs));
SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);

SDValue Ops[] = {RegSeq,
Expand Down Expand Up @@ -2341,7 +2340,7 @@ void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(2, NumVecs));

if (Narrow)
transform(Regs, Regs.begin(),
Expand Down Expand Up @@ -2379,7 +2378,7 @@ void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(1, NumVecs));

if (Narrow)
transform(Regs, Regs.begin(),
Expand Down Expand Up @@ -2433,7 +2432,7 @@ void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
bool Narrow = VT.getSizeInBits() == 64;

// Form a REG_SEQUENCE to force register allocation.
SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
SmallVector<SDValue, 4> Regs(N->ops().slice(2, NumVecs));

if (Narrow)
transform(Regs, Regs.begin(),
Expand Down