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[RISCV] Combine 3 bit-manip extensions into B #132858

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Merged
merged 1 commit into from
Mar 25, 2025

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a4lg
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@a4lg a4lg commented Mar 25, 2025

Like cryptography extensions like Zk, B (a combination of Zba, Zbb and Zbs extensions) can be useful if we handle this extension as a combination.
If all Zba, Zbb and Zbs extensions are enabled, it also enables the B extension.

Like cryptography extensions like "Zk", "B" (a combination of "Zba", "Zbb"
and "Zbs" extensions) can be useful if we handle this extension as a
combination.

If all "Zba", "Zbb" and "Zbs" extensions are enabled, it also enables
the "B" extension.
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llvmbot commented Mar 25, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Tsukasa OI (a4lg)

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Like cryptography extensions like Zk, B (a combination of Zba, Zbb and Zbs extensions) can be useful if we handle this extension as a combination.
If all Zba, Zbb and Zbs extensions are enabled, it also enables the B extension.


Full diff: https://github.com/llvm/llvm-project/pull/132858.diff

2 Files Affected:

  • (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-2)
  • (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 0f7673c624c92..fefd173f6675e 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -878,8 +878,8 @@ void RISCVISAInfo::updateImplication() {
 }
 
 static constexpr StringLiteral CombineIntoExts[] = {
-    {"zk"},    {"zkn"},  {"zks"},   {"zvkn"},  {"zvknc"},
-    {"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
+    {"b"},     {"zk"},    {"zkn"},  {"zks"},   {"zvkn"},
+    {"zvknc"}, {"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"},
 };
 
 void RISCVISAInfo::updateCombination() {
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index b1793233339de..44585f95ef676 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
 ; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s
+; RUN: llc -mtriple=riscv32 -mattr=+zba,+zbb,+zbs %s -o - | FileCheck --check-prefixes=CHECK,RV32COMBINEINTOB %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
@@ -173,6 +174,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+a --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a,experimental-zalasr --riscv-abi-attributes %s -o - | FileCheck --check-prefixes=CHECK,RV64ZALASRA,A7 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
+; RUN: llc -mtriple=riscv64 -mattr=+zba,+zbb,+zbs %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -341,6 +343,7 @@
 ; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
 ; RV32A: .attribute 5, "rv32i2p1_a2p1_zaamo1p0_zalrsc1p0"
 ; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
+; RV32COMBINEINTOB: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
 ; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
 ; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
 ; RV32C: .attribute 5, "rv32i2p1_c2p0_zca1p0"
@@ -505,6 +508,7 @@
 ; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
 ; RV64A: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalrsc1p0"
 ; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
+; RV64COMBINEINTOB: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
 ; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
 ; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
 ; RV64C: .attribute 5, "rv64i2p1_c2p0_zca1p0"

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@lenary lenary left a comment

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LGTM. Please wait for a second reviewer, because this logic does impact a lot of places in the toolchain.

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LGTM

My only concern is that this will break what versions of binutils we can use with -fno-integrated-as. But I'm tired of raising this on every patch like this where an older extension name needs to imply a newer extension name. So I'm going to stop.

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I'm OK with this, just have a concern about compatibility (we have the discussion in #76893 (comment) as well).

@wangpc-pp wangpc-pp requested a review from kito-cheng March 25, 2025 06:31
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@kito-cheng kito-cheng left a comment

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LGTM, I am happy with this of cause :P

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@a4lg let us know if you don't have commit right, we can help you on merge this :)

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a4lg commented Mar 25, 2025

@kito-cheng Yes, I'm not a LLVM committer. So could you merge that?

@kito-cheng kito-cheng merged commit a6de034 into llvm:main Mar 25, 2025
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